Commit 2cab0c1063 for qemu.org
commit 2cab0c10632960c01972727608196984d52c93bf
Merge: 62c31d1b6a 269cab810c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Fri Oct 16 07:49:38 2026 +0200
Merge tag 'pbouvier/pr/multi_target-20261015' of https://gitlab.com/p-b-o/qemu into staging
Changes:
- [PATCH v3 00/12] multi-target: add hexagon (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
Link: https://lore.kernel.org/qemu-devel/20261014210526.104215-1-pierrick.bouvier@oss.qualcomm.com
- [PATCH 0/8] multi-target: remove qmp_query_cpu_definitions duplication (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
Link: https://lore.kernel.org/qemu-devel/20261015005355.62406-1-pierrick.bouvier@oss.qualcomm.com
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# gpg: Signature made Thu 15 Oct 2026 09:31:06 PM CEST
# gpg: using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197 3FDB B444 37D1 9C28 62DF
* tag 'pbouvier/pr/multi_target-20261015' of https://gitlab.com/p-b-o/qemu:
qmp: reimplement qmp_query_cpu_definitions as a dispatcher function
target/s390x: rename qmp_query_cpu_definitions to qmp_query_s390x_cpu_definitions
target/riscv: rename to qmp_query_cpu_definitions to qmp_query_riscv_cpu_definitions
target/ppc: rename qmp_query_cpu_definitions to qmp_query_ppc_cpu_definitions
target/mips: rename qmp_query_cpu_definitions to qmp_query_mips_cpu_definitions
target/loongarch: rename to qmp_query_loongarch_cpu_definitions
target/i386: rename qmp_query_cpu_definitions to qmp_query_i386_cpu_definitions
target/arm: rename qmp_query_cpu_definitions to qmp_query_arm_cpu_definitions
meson.build: add hexagon-softmmu to multi-target
semihosting: remove common_* functions
semihosting: use new semihosting ops
target/arm: declare semihosting ops
target/hexagon: declare semihosting ops
target/riscv: declare semihosting ops
target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl
semihosting: declare semihosting cpu ops
hw/core/cpu: restrict tcg_ops to CONFIG_TCG only
hw/hexagon/virt: make machine available for hexagon target only
target-info: add target_hexagon
target/hexagon: prefix helpers conflicting with other arch
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>