Commit 5ccda18d1ba2 for kernel

commit 5ccda18d1ba2ecf436102a211baf1fbd5d81703f
Merge: fd179f8a05be 24b620729e53
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Sep 27 08:15:58 2026 -0700

    Merge tag 'perf-urgent-2026-09-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

    Pull perf events fixes from Ingo Molnar:

     - Fixes for KVM guest PEBS virtualization (Sean Christopherson)

     - Fixes for various Intel PMUs related to PEBS data-source (Dapeng Mi)

     - Fix Intel Panther Cove event scheduling constraints (Dapeng Mi)

     - Fix Intel DMR/NVL OMR extra registers event scheduling (Dapeng Mi)

     - Rename two confusingly named PMU attributes (Dapeng Mi)

     - Fix a refcount leak in attach_perf_ctx_data() (Namhyung Kim)

     - Fix NULL pointer dereference crash in __perf_pmu_sched_task()
       (Puranjay Mohan)

     - Fix CPU-wide event scheduling (Puranjay Mohan)

     - Fix x86 LBR branch entry generation (Puranjay Mohan)

    * tag 'perf-urgent-2026-09-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
      perf/core: Fill branch entries with a single assignment
      perf/core: Run sched_task() for PMUs with only CPU-wide events
      perf/core: Fix NULL pmu_ctx passed to pmu->sched_task()
      perf/core: Fix a refcount leak in attach_perf_ctx_data()
      perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp
      perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp
      perf/x86/intel: Fix precise OMR event scheduling for DMR/NVL
      perf/x86/intel: Constrain Panther Cove UOPS_DISPATCHED events to PMCs 0-3
      perf/x86/intel: Delete dead NVL PEBS data-source initcall
      perf/x86/intel: Fix Panther Cove PEBS data-source snoop states
      perf/x86/intel: Remove incorrect Panther Cove PEBS data-source constraints
      perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints
      perf/x86/intel: Update arw_latency_data() mem-op direction handling
      perf/x86/intel: Fix DKT PEBS load/store direction for latency events, to fix sample classification
      perf/x86/intel: Fix CMT PEBS load/store direction for latency events, to fix sample classification
      perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification
      perf/x86/intel: Make @data a mandatory param for intel_guest_get_msrs()
      perf/x86/intel: Don't pointlessly context switch DS_AREA (and PEBS config) if PEBS is unused
      perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU has PEBS isolation, to fix stuck PEBS_ENABLED
      perf/x86/intel: Ensure KVM guest PEBS path doesn't set unwanted PERF_GLOBAL_CTRL bits