Commit a19f59a72d for qemu.org
commit a19f59a72d96056d9a8f48cf6c77f5787491e414
Merge: 2cab0c1063 34c91feed0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Fri Oct 16 07:50:02 2026 +0200
Merge tag 'pull-hex-20261015' of https://github.com/qualcomm/qemu into staging
Hexagon: bugfixes + pcycle support
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmrRMWYACgkQGlSvuOVk
# bDJBLA//WjANahTrYpC1WDwR1/kVhlbvUfQxuqR/XS4TE2xwRiNw2ZCGxC6IHXD+
# Qw/65lwodATXEIjtKGCjZ0tgsG6eKCixn9d24VSx1TJW9wgWzPnh0qlj+0e7Jo+o
# bQDdmsPwHxbGJk8PzI3i6BWntIky4WaffLBkav5H6kRXUvue48dRQp/OCkLn1ljg
# 31+j8dK/E74BJcymAH2rn0UhHI+8b5hIG0TJjJ7ydICPLYw7UDJpsfEQEApNJ4eW
# VcY6/GAJ4OQzWcNAMexLYb8yscVNdef3F5v5z9iq6q8oiC6hMrTta++2coUXyUTu
# 10M4HMBtRhW9RXnYP4y3iiDnf3PzMriCc2tfkW6a+JlRbQ7KzmGzTfztuI04b4VQ
# UC/6pcg3hN+kp3JSxEvZ5MMWlJU3bNjvrFJ+DJGxZUG1bRbj4IOpXhMAZx0IEuok
# rWet9/Mhg4hH5Gwy2i7IEDw7ZGXKZMLIXcx9q+dYxAeK/LqnDbTXQfdI7D7Xo7Lz
# 98apTsmC2HDvUmVOqhbiys91XhhYJ7povyNrljrcrCnzKjlhlYOUsZgf331fgfY+
# KuoFaKGWgmU4nj3h2fun4Symv92wJSc6q9LToZtDBekJSlnRDL71YyZ8kShZxPT4
# Vvqb6J8syU2xhNnf1HRIC3U6G/aZM/k5tszylcHmDtZx4c7bXlk=
# =CVab
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 15 Oct 2026 10:02:46 PM CEST
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg: aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20261015' of https://github.com/qualcomm/qemu:
tests/functional/hexagon: add MiniVM, lock tests
target/hexagon: set a started thread's enable bit when start retires
target/hexagon: halt on tlblock when the TLB lock is contended
target/hexagon: wake K0 and TLB lock waiters
target/hexagon: check privilege mode for system instructions
exec: correct translator_io_start documentation
target/hexagon: mark clock-backed register reads as I/O
hw/hexagon: model PCYCLE with virtual clock
target/hexagon: remove packet-count PCYCLE implementation
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>