Commit a1b99e787d for qemu.org
commit a1b99e787d956b7f0fb19de30cfade43d9bfb59d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Fri Jul 31 11:56:18 2026 -0700
target/s390x/tcg: Convert op_ld32s to op_ld
Note that op_ld32s already or'd in insn->data, with the only
use being MO_ALIGN. We now put the entire MemOp in insn->data.
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260731185628.23161-6-richard.henderson@linaro.org>
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 23b00a0eeb..69d5114f24 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -418,12 +418,12 @@
/* LOAD */
C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0)
- D(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0, 0)
- D(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0, 0)
+ D(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld, 0, MO_BESL)
+ D(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld, 0, MO_BESL)
C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0)
C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0)
D(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0, 0)
- D(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0, 0)
+ D(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld, 0, MO_BESL)
F(0x2800, LDR, RR_a, Z, 0, f2, 0, f1, mov2, 0, IF_AFP1 | IF_AFP2)
F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
F(0xed65, LDY, RXY_a, LD, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
@@ -434,9 +434,9 @@
/* LOAD IMMEDIATE */
C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0)
/* LOAD RELATIVE LONG */
- D(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0, MO_ALIGN)
+ D(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld, 0, MO_BESL | MO_ALIGN)
D(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0, MO_ALIGN)
- D(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0, MO_ALIGN)
+ D(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld, 0, MO_BESL | MO_ALIGN)
/* LOAD ADDRESS */
C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0)
C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0)
@@ -464,9 +464,9 @@
C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32)
C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64)
C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64)
- D(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64, 0)
+ D(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld, s64, MO_BESL)
D(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64, 0)
- D(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64, 0)
+ D(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld, s64, MO_BESL)
F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP)
F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP)
F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index b724db6a1c..42b208a3ca 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2755,13 +2755,6 @@ static DisasJumpType op_ld(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
-static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)
-{
- tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),
- MO_BESL | s->insn->data);
- return DISAS_NEXT;
-}
-
static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),