Commit c07a0960f1 for ffmpeg
commit c07a0960f1c43258e421c5fc05b15bfe6756386f
Author: Zuxy Meng <zuxy.meng@gmail.com>
Date: Mon Nov 2 21:10:20 2026 -0800
avcodec/x86/vp9: convert dc/dc_top/dc_left 4x4_16 predictors MMXEXT to SSE2
Convert the 16-bit DC 4x4 predictors (dc, dc_top and dc_left,
the latter two sharing the DC_1D_FNS macro) from MMXEXT to XMM.
The EXTERNAL_MMXEXT block in vp9dsp_init_16bpp.c is now empty
and removed.
Benchmarks (checkasm, Zen 4, pinned, median of 3
interleaved pairs, cycles):
vp9_dc_4x4_10bpp: 1.1 -> 0.9
vp9_dc_4x4_12bpp: 1.1 -> 0.9
vp9_dc_left_4x4_10bpp: 1.0 -> 0.4
vp9_dc_left_4x4_12bpp: 0.9 -> 0.4
vp9_dc_top_4x4_10bpp: 1.0 -> 0.5
vp9_dc_top_4x4_12bpp: 1.0 -> 0.5
checkasm --test=vp9dsp passes (1272/1272 over 3 seeds).
Signed-off-by: Zuxy Meng <zuxy.meng@gmail.com>
diff --git a/libavcodec/x86/vp9dsp_init_16bpp.c b/libavcodec/x86/vp9dsp_init_16bpp.c
index 18c7006eb7..bc47529094 100644
--- a/libavcodec/x86/vp9dsp_init_16bpp.c
+++ b/libavcodec/x86/vp9dsp_init_16bpp.c
@@ -45,9 +45,9 @@ decl_fpel_func(avg, 128, _16, avx2);
decl_ipred_fns(v, 16, sse, sse);
decl_ipred_fns(h, 16, sse2, sse2);
-decl_ipred_fns(dc, 16, mmxext, sse2);
-decl_ipred_fns(dc_top, 16, mmxext, sse2);
-decl_ipred_fns(dc_left, 16, mmxext, sse2);
+decl_ipred_fns(dc, 16, sse2, sse2);
+decl_ipred_fns(dc_top, 16, sse2, sse2);
+decl_ipred_fns(dc_left, 16, sse2, sse2);
decl_ipred_fn(dl, 16, 16, avx2);
decl_ipred_fn(dl, 32, 16, avx2);
decl_ipred_fn(dr, 16, 16, avx2);
@@ -71,12 +71,6 @@ av_cold void ff_vp9dsp_init_16bpp_x86(VP9DSPContext *dsp)
{
int cpu_flags = av_get_cpu_flags();
- if (EXTERNAL_MMXEXT(cpu_flags)) {
- init_ipred_func(dc, DC, 4, 16, mmxext);
- init_ipred_func(dc_top, TOP_DC, 4, 16, mmxext);
- init_ipred_func(dc_left, LEFT_DC, 4, 16, mmxext);
- }
-
if (EXTERNAL_SSE(cpu_flags)) {
init_fpel_func(3, 0, 16, put, , sse);
init_fpel_func(2, 0, 32, put, , sse);
@@ -94,9 +88,9 @@ av_cold void ff_vp9dsp_init_16bpp_x86(VP9DSPContext *dsp)
init_fpel_func(1, 1, 64, avg, _16, sse2);
init_fpel_func(0, 1, 128, avg, _16, sse2);
init_ipred_funcs(h, HOR, 16, sse2);
- init_8_16_32_ipred_funcs(dc, DC, 16, sse2);
- init_8_16_32_ipred_funcs(dc_top, TOP_DC, 16, sse2);
- init_8_16_32_ipred_funcs(dc_left, LEFT_DC, 16, sse2);
+ init_ipred_funcs(dc, DC, 16, sse2);
+ init_ipred_funcs(dc_top, TOP_DC, 16, sse2);
+ init_ipred_funcs(dc_left, LEFT_DC, 16, sse2);
init_ipred_funcs(dl, DIAG_DOWN_LEFT, 16, sse2);
init_ipred_funcs(dr, DIAG_DOWN_RIGHT, 16, sse2);
init_ipred_funcs(vl, VERT_LEFT, 16, sse2);
diff --git a/libavcodec/x86/vp9intrapred_16bpp.asm b/libavcodec/x86/vp9intrapred_16bpp.asm
index 91eb181aa9..196e53fe10 100644
--- a/libavcodec/x86/vp9intrapred_16bpp.asm
+++ b/libavcodec/x86/vp9intrapred_16bpp.asm
@@ -254,22 +254,23 @@ cglobal vp9_ipred_h_32x32_16, 3, 5, 4, dst, stride, l, stride3, cnt
jge .loop
RET
-INIT_MMX mmxext
+INIT_XMM sse2
cglobal vp9_ipred_dc_4x4_16, 4, 4, 2, dst, stride, l, a
- mova m0, [lq]
- paddw m0, [aq]
+ movq m0, [lq]
+ movq m1, [aq]
+ paddw m0, m1
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
pmaddwd m0, [pw_1]
- pshufw m1, m0, q3232
+ pshuflw m1, m0, q3232
paddd m0, [pd_4]
paddd m0, m1
psrad m0, 3
- pshufw m0, m0, q0000
- mova [dstq+strideq*0], m0
- mova [dstq+strideq*1], m0
- mova [dstq+strideq*2], m0
- mova [dstq+stride3q ], m0
+ pshuflw m0, m0, 0
+ movq [dstq+strideq*0], m0
+ movq [dstq+strideq*1], m0
+ movq [dstq+strideq*2], m0
+ movq [dstq+stride3q ], m0
RET
INIT_XMM sse2
@@ -367,21 +368,21 @@ cglobal vp9_ipred_dc_32x32_16, 4, 4, 2, dst, stride, l, a
RET
%macro DC_1D_FNS 2
-INIT_MMX mmxext
+INIT_XMM sse2
cglobal vp9_ipred_dc_%1_4x4_16, 4, 4, 2, dst, stride, l, a
- mova m0, [%2]
+ movq m0, [%2]
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
pmaddwd m0, [pw_1]
- pshufw m1, m0, q3232
+ pshuflw m1, m0, q3232
paddd m0, [pd_2]
paddd m0, m1
psrad m0, 2
- pshufw m0, m0, q0000
- mova [dstq+strideq*0], m0
- mova [dstq+strideq*1], m0
- mova [dstq+strideq*2], m0
- mova [dstq+stride3q ], m0
+ pshuflw m0, m0, 0
+ movq [dstq+strideq*0], m0
+ movq [dstq+strideq*1], m0
+ movq [dstq+strideq*2], m0
+ movq [dstq+stride3q ], m0
RET
INIT_XMM sse2