Commit ec4bc137f7 for qemu.org

commit ec4bc137f74a03dbf8bb7c2af494c2af0b7df57c
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date:   Tue Sep 29 21:24:27 2026 +0000

    tests/tcg/mips/include/wrappers_mips64r6.h: add missing wrappers for and, nor, or, xor insn

    Acked-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Link: https://lore.kernel.org/qemu-devel/20260929212439.110454-13-pierrick.bouvier@oss.qualcomm.com
    Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

diff --git a/tests/tcg/mips/include/wrappers_mips64r6.h b/tests/tcg/mips/include/wrappers_mips64r6.h
index 33d03de50b..f078f534f0 100644
--- a/tests/tcg/mips/include/wrappers_mips64r6.h
+++ b/tests/tcg/mips/include/wrappers_mips64r6.h
@@ -47,7 +47,6 @@ DO_MIPS64R6__RD__RS(DCLZ, dclz)
 DO_MIPS64R6__RD__RS(BITSWAP, bitswap)
 DO_MIPS64R6__RD__RS(DBITSWAP, dbitswap)

-
 #define DO_MIPS64R6__RD__RS_RT(suffix, mnemonic)                       \
 static inline void do_mips64r6_##suffix(const void *input1,            \
                                         const void *input2,            \
@@ -80,6 +79,11 @@ DO_MIPS64R6__RD__RS_RT(DMUH, dmuh)
 DO_MIPS64R6__RD__RS_RT(DMULU, dmulu)
 DO_MIPS64R6__RD__RS_RT(DMUHU, dmuhu)

+DO_MIPS64R6__RD__RS_RT(AND, and)
+DO_MIPS64R6__RD__RS_RT(NOR, nor)
+DO_MIPS64R6__RD__RS_RT(OR, or)
+DO_MIPS64R6__RD__RS_RT(XOR, xor)
+

 #define DO_MIPS64R6__RT__RS_RT(suffix, mnemonic)                       \
 static inline void do_mips64r6_##suffix(const void *input1,            \