Commit 13c916af3abf for kernel

commit 13c916af3abf98f4a2a00b9463d2fc00cc6bc00e
Merge: ca4ee40bf13d 5921ae27ea7b
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Feb 15 08:18:57 2026 -0800

    Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

    Pull clk updates from Stephen Boyd:
     "Not much changed in the clk framework this time except the clk.h
      consumer API moved the context saving APIs around to fix a build error
      in certain configurations.

      There was a change to the core framework for CLK_OPS_PARENT_ENABLE
      behavior during registration, but it wrecked existing drivers that
      didn't expect things to be turned off during clk registration so it
      got reverted.

      This cycle is really a large collection of new clk drivers, primarily
      for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
      Another big change in here is support for automatic hardware clock
      gating on Samsung SoCs where the clks turn on and off when needed.
      Ideally more vendors move to this method for better power savings. The
      highlights are in the updates section below.

      Beyond all the new drivers we have a bunch of cleanups like converting
      drivers from divider_round_rate() to divider_determine_rate() and
      using scoped for each OF child loops. Otherwise it's the usual data
      fixes and plugging reference leaks, etc. that's all pretty ordinary
      but not critical enough to fix until the next release.

      New Drivers:
       - Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
         video clk controllers
       - Qualcomm SM8750 camera clk controllers
       - Qualcomm MSM8940 and SDM439 global clk controllers
       - Google GS101 Display Process Unit (DPU) clk controllers
       - SpacemiT K3 clk controllers
       - Amlogic t7 clk controllers
       - Aspeed AST2700 clk controllers

      Updates:
       - Convert clock dividers from round_rate() to determine_rate()
       - Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
       - Automatic hardware clk gating on Google GS101 SoCs
       - Amlogic s4 video clks
       - CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
         RZ/V2N
       - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
         Renesas RZ/T21H and RZ/N2H
       - DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
         resets on Renesas RZ/V2N
       - More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
       - CPU frequency scaling on T-HEAD TH1520"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
      clk: aspeed: Add reset for HACE/VIDEO
      dt-bindings: clock: aspeed: Add VIDEO reset definition
      clk: aspeed: add AST2700 clock driver
      MAINTAINERS: Add entry for ASPEED clock drivers.
      clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
      Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
      clk: Disable KUNIT_UML_PCI
      dt-bindings: clk: rs9: Fix DIF pattern match
      clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
      clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
      clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
      clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
      clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
      clk: mediatek: Fix error handling in runtime PM setup
      clk: mediatek: don't select clk-mt8192 for all ARM64 builds
      clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
      clk: mediatek: Refactor pllfh registration to pass device
      clk: mediatek: Pass device to clk_hw_register for PLLs
      clk: mediatek: Refactor pll registration to pass device
      clk: Respect CLK_OPS_PARENT_ENABLE during recalc
      ...