Commit 14ecbe9fb2 for qemu.org
commit 14ecbe9fb27f9f954f6c937a6e98c3eb39433c75
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: Mon Sep 1 12:08:06 2025 +0800
hw/intc/aspeed: Remove GIC 128 - 136
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 6d6ffe3127..d17f446661 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -153,20 +153,17 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_SDHCI] = 197,
};
-/* GICINT 128 */
/* GICINT 192 */
-static const int ast2700_gic128_gic192_intcmap[] = {
+static const int ast2700_gic192_intcmap[] = {
[ASPEED_DEV_LPC] = 0,
[ASPEED_DEV_IBT] = 2,
[ASPEED_DEV_KCS] = 4,
};
-/* GICINT 129 */
/* GICINT 193 */
-/* GICINT 130 */
/* GICINT 194 */
-static const int ast2700_gic130_gic194_intcmap[] = {
+static const int ast2700_gic194_intcmap[] = {
[ASPEED_DEV_I2C] = 0,
[ASPEED_DEV_ADC] = 16,
[ASPEED_DEV_GPIO] = 18,
@@ -174,18 +171,16 @@ static const int ast2700_gic130_gic194_intcmap[] = {
[ASPEED_DEV_SGPIOM1] = 24,
};
-/* GICINT 131 */
/* GICINT 195 */
-static const int ast2700_gic131_gic195_intcmap[] = {
+static const int ast2700_gic195_intcmap[] = {
[ASPEED_DEV_I3C] = 0,
[ASPEED_DEV_WDT] = 16,
[ASPEED_DEV_FMC] = 25,
[ASPEED_DEV_PWM] = 29,
};
-/* GICINT 132 */
/* GICINT 196 */
-static const int ast2700_gic132_gic196_intcmap[] = {
+static const int ast2700_gic196_intcmap[] = {
[ASPEED_DEV_ETH1] = 0,
[ASPEED_DEV_ETH2] = 1,
[ASPEED_DEV_ETH3] = 2,
@@ -206,14 +201,12 @@ static const int ast2700_gic132_gic196_intcmap[] = {
[ASPEED_DEV_PCIE2] = 31,
};
-/* GICINT 133 */
/* GICINT 197 */
-static const int ast2700_gic133_gic197_intcmap[] = {
+static const int ast2700_gic197_intcmap[] = {
[ASPEED_DEV_SDHCI] = 1,
[ASPEED_DEV_PECI] = 4,
};
-/* GICINT 128 ~ 136 */
/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
@@ -223,25 +216,16 @@ struct gic_intc_irq_info {
};
static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
- {192, 1, 0, ast2700_gic128_gic192_intcmap},
+ {192, 1, 0, ast2700_gic192_intcmap},
{193, 1, 1, NULL},
- {194, 1, 2, ast2700_gic130_gic194_intcmap},
- {195, 1, 3, ast2700_gic131_gic195_intcmap},
- {196, 1, 4, ast2700_gic132_gic196_intcmap},
- {197, 1, 5, ast2700_gic133_gic197_intcmap},
+ {194, 1, 2, ast2700_gic194_intcmap},
+ {195, 1, 3, ast2700_gic195_intcmap},
+ {196, 1, 4, ast2700_gic196_intcmap},
+ {197, 1, 5, ast2700_gic197_intcmap},
{198, 1, 6, NULL},
{199, 1, 7, NULL},
{200, 1, 8, NULL},
{201, 1, 9, NULL},
- {128, 0, 1, ast2700_gic128_gic192_intcmap},
- {129, 0, 2, NULL},
- {130, 0, 3, ast2700_gic130_gic194_intcmap},
- {131, 0, 4, ast2700_gic131_gic195_intcmap},
- {132, 0, 5, ast2700_gic132_gic196_intcmap},
- {133, 0, 6, ast2700_gic133_gic197_intcmap},
- {134, 0, 7, NULL},
- {135, 0, 8, NULL},
- {136, 0, 9, NULL},
};
static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
@@ -285,8 +269,7 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
}
/*
- * Invalid OR gate index, device IRQ should be between 128 to 136
- * and 192 to 201.
+ * Invalid OR gate index, device IRQ should be between 192 to 201.
*/
g_assert_not_reached();
}
@@ -701,7 +684,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
/* INTC -> GIC192 - GIC201 */
- /* INTC -> GIC128 - GIC136 */
for (i = 0; i < ic->num_outpins; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->gic),
@@ -901,13 +883,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/*
* The AST2700 I2C controller has one source INTC per bus.
*
- * For AST2700 A0:
- * I2C bus interrupts are connected to the OR gate from bit 0 to bit
- * 15, and the OR gate output pin is connected to the input pin of
- * GICINT130 of INTC (CPU Die). Then, the output pin is connected to
- * the GIC.
- *
- * For AST2700 A1:
* I2C bus interrupts are connected to the OR gate from bit 0 to bit
* 15, and the OR gate output pin is connected to the input pin of
* GICINT194 of INTCIO (IO Die). Then, the output pin is connected
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index f14c340b60..ad95d76543 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -21,24 +21,6 @@
* because its memory region is start at 0x1000
*
*/
-REG32(GICINT128_EN, 0x000)
-REG32(GICINT128_STATUS, 0x004)
-REG32(GICINT129_EN, 0x100)
-REG32(GICINT129_STATUS, 0x104)
-REG32(GICINT130_EN, 0x200)
-REG32(GICINT130_STATUS, 0x204)
-REG32(GICINT131_EN, 0x300)
-REG32(GICINT131_STATUS, 0x304)
-REG32(GICINT132_EN, 0x400)
-REG32(GICINT132_STATUS, 0x404)
-REG32(GICINT133_EN, 0x500)
-REG32(GICINT133_STATUS, 0x504)
-REG32(GICINT134_EN, 0x600)
-REG32(GICINT134_STATUS, 0x604)
-REG32(GICINT135_EN, 0x700)
-REG32(GICINT135_STATUS, 0x704)
-REG32(GICINT136_EN, 0x800)
-REG32(GICINT136_STATUS, 0x804)
REG32(GICINT192_201_EN, 0xB00)
REG32(GICINT192_201_STATUS, 0xB04)
@@ -507,29 +489,9 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
trace_aspeed_intc_write(name, offset, size, data);
switch (reg) {
- case R_GICINT128_EN:
- case R_GICINT129_EN:
- case R_GICINT130_EN:
- case R_GICINT131_EN:
- case R_GICINT132_EN:
- case R_GICINT133_EN:
- case R_GICINT134_EN:
- case R_GICINT135_EN:
- case R_GICINT136_EN:
case R_GICINT192_201_EN:
aspeed_intc_enable_handler(s, offset, data);
break;
- case R_GICINT128_STATUS:
- case R_GICINT129_STATUS:
- case R_GICINT130_STATUS:
- case R_GICINT131_STATUS:
- case R_GICINT132_STATUS:
- case R_GICINT133_STATUS:
- case R_GICINT134_STATUS:
- case R_GICINT135_STATUS:
- case R_GICINT136_STATUS:
- aspeed_intc_status_handler(s, offset, data);
- break;
case R_GICINT192_201_STATUS:
aspeed_intc_status_handler_multi_outpins(s, offset, data);
break;
@@ -891,15 +853,6 @@ static const TypeInfo aspeed_intc_info = {
static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
{0, 0, 10, R_GICINT192_201_EN, R_GICINT192_201_STATUS},
- {1, 10, 1, R_GICINT128_EN, R_GICINT128_STATUS},
- {2, 11, 1, R_GICINT129_EN, R_GICINT129_STATUS},
- {3, 12, 1, R_GICINT130_EN, R_GICINT130_STATUS},
- {4, 13, 1, R_GICINT131_EN, R_GICINT131_STATUS},
- {5, 14, 1, R_GICINT132_EN, R_GICINT132_STATUS},
- {6, 15, 1, R_GICINT133_EN, R_GICINT133_STATUS},
- {7, 16, 1, R_GICINT134_EN, R_GICINT134_STATUS},
- {8, 17, 1, R_GICINT135_EN, R_GICINT135_STATUS},
- {9, 18, 1, R_GICINT136_EN, R_GICINT136_STATUS},
};
static void aspeed_2700_intc_class_init(ObjectClass *klass, const void *data)
@@ -909,8 +862,8 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, const void *data)
dc->desc = "ASPEED 2700 INTC Controller";
aic->num_lines = 32;
- aic->num_inpins = 10;
- aic->num_outpins = 19;
+ aic->num_inpins = 1;
+ aic->num_outpins = 10;
aic->mem_size = 0x4000;
aic->nr_regs = 0xB08 >> 2;
aic->reg_offset = 0x1000;