Commit 1d8416f58a for qemu.org

commit 1d8416f58a92af4f4166f8fbd18fd97c5979ee6e
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date:   Wed Jun 3 04:00:40 2026 +0000

    hw/arm/aspeed_ast1040: Reuse AST2700 watchdog models

    Instantiate and realize the watchdog models for the AST1040 SoC.

    The AST1040 watchdog controller is compatible with the AST2700 watchdog
    controller, so reuse the existing AST2700 watchdog model.

    Configure the AST1040 SoC with 8 watchdog instances and map them to
    their corresponding MMIO regions. The first watchdog controller (WDT0) is
    located at 0x74c37000, with subsequent watchdogs placed according to the
    controller register space size.

    Each watchdog is linked to the SCU device before realization to provide the
    required reset and system control interactions.

    Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
    Reviewed-by: Cédric Le Goater <clg@redhat.com>
    Link: https://lore.kernel.org/qemu-devel/20260603040027.938816-11-jamin_lin@aspeedtech.com
    Signed-off-by: Cédric Le Goater <clg@redhat.com>

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index 6d1cb9b102..57ffc0807a 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -119,6 +119,11 @@ static void aspeed_soc_ast1040_init(Object *obj)
     }
     object_initialize_child(obj, "i2c", &s->i2c, TYPE_ASPEED_1040_I2C);

+    for (i = 0; i < sc->wdts_num; i++) {
+        object_initialize_child(obj, "wdt[*]", &s->wdt[i],
+                                "aspeed.wdt-ast2700");
+    }
+
     object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
@@ -249,6 +254,19 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
     }

+    /* Watch dog */
+    for (i = 0; i < sc->wdts_num; i++) {
+        AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
+
+        object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+                                 &error_abort);
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+            return;
+        }
+        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+    }
+
     /* Unimplemented peripherals */
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
                                   "aspeed.pwm",
@@ -290,6 +308,7 @@ static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
     sc->sram_size[1]    = 16 * MiB; /* Hyper RAM */
     sc->uarts_num       = 13;
     sc->sgpio_num       = 2;
+    sc->wdts_num        = 8;
     sc->uarts_base      = ASPEED_DEV_UART0;
     sc->irqmap          = aspeed_soc_ast1040_irqmap;
     sc->memmap          = aspeed_soc_ast1040_memmap;