Commit 1e0ea4dff0f4 for kernel

commit 1e0ea4dff0f46a3575b6882941dc7331c232d72c
Merge: c22e26bd0906 ad0956366046
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Wed Feb 11 16:36:08 2026 -0800

    Merge tag 'iommu-updates-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux

    Pull iommu updates from Joerg Roedel:
     "Core changes:
       - Rust bindings for IO-pgtable code
       - IOMMU page allocation debugging support
       - Disable ATS during PCI resets

      Intel VT-d changes:
       - Skip dev-iotlb flush for inaccessible PCIe device
       - Flush cache for PASID table before using it
       - Use right invalidation method for SVA and NESTED domains
       - Ensure atomicity in context and PASID entry updates

      AMD-Vi changes:
       - Support for nested translations
       - Other minor improvements

      ARM-SMMU-v2 changes:
       - Configure SoC-specific prefetcher settings for Qualcomm's "MDSS"

      ARM-SMMU-v3 changes:
       - Improve CMDQ locking fairness for pathetically small queue sizes
       - Remove tracking of the IAS as this is only relevant for AArch32 and
         was causing C_BAD_STE errors
       - Add device-tree support for NVIDIA's CMDQV extension
       - Allow some hitless transitions for the 'MEV' and 'EATS' STE fields
       - Don't disable ATS for nested S1-bypass nested domains
       - Additions to the kunit selftests"

    * tag 'iommu-updates-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (54 commits)
      iommupt: Always add IOVA range to iotlb_gather in gather_range_pages()
      iommu/amd: serialize sequence allocation under concurrent TLB invalidations
      iommu/amd: Fix type of type parameter to amd_iommufd_hw_info()
      iommu/arm-smmu-v3: Do not set disable_ats unless vSTE is Translate
      iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage
      iommu/arm-smmu-v3: Mark EATS_TRANS safe when computing the update sequence
      iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence
      iommu/arm-smmu-v3: Add update_safe bits to fix STE update sequence
      iommu/arm-smmu-v3: Add device-tree support for CMDQV driver
      iommu/tegra241-cmdqv: Decouple driver from ACPI
      iommu/arm-smmu-qcom: Restore ACTLR settings for MDSS on sa8775p
      iommu/vt-d: Fix race condition during PASID entry replacement
      iommu/vt-d: Clear Present bit before tearing down context entry
      iommu/vt-d: Clear Present bit before tearing down PASID entry
      iommu/vt-d: Flush piotlb for SVM and Nested domain
      iommu/vt-d: Flush cache for PASID table before using it
      iommu/vt-d: Flush dev-IOTLB only when PCIe device is accessible in scalable mode
      iommu/vt-d: Skip dev-iotlb flush for inaccessible PCIe device without scalable mode
      rust: iommu: fix `srctree` link warning
      rust: iommu: fix Rust formatting
      ...