Commit 1fa6375af2 for qemu.org

commit 1fa6375af2454e7cb1ccdd731cfd02498a37b432
Author: Philippe Mathieu-Daudé <philmd@mailo.com>
Date:   Wed May 13 11:25:23 2026 +0200

    target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type

    Commit 676624d757a ("target/arm/tcg: refine cache descriptions
    with a wrapper") added the make_ccsidr() helper. Use it. Besides
    being simpler to review, it also makes arm_max_initfn() more in
    line which aarch64_a57_initfn(), which it almost duplicates.

    Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
    Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
    Acked-by: Peter Maydell <peter.maydell@linaro.org>
    Message-Id: <20260526203722.79463-11-philmd@linaro.org>

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 919ed8a6cf..cf643ce43b 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -9,6 +9,7 @@
  */

 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "cpu.h"
 #include "accel/tcg/cpu-ops.h"
 #include "internals.h"
@@ -756,9 +757,12 @@ static void arm_max_initfn(Object *obj)
     SET_IDREG(isar, ID_ISAR6, 0);
     cpu->isar.reset_pmcr_el0 = 0x41013000;
     SET_IDREG(isar, CLIDR, 0x0a200023);
-    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    /* 32KB L1 dcache */
+    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
+    /* 48KB L1 icache */
+    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
+    /* 2048KB L2 cache */
+    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
     define_cortex_a72_a57_a53_cp_reginfo(cpu);

     aa32_max_features(cpu);