Commit 26154585c6 for qemu.org
commit 26154585c69c9fde612d78a1adeddb3ea71e24ce
Author: Roan Richmond <roan.richmond@codethink.co.uk>
Date: Wed Nov 12 16:29:21 2025 +0000
Add RISCV ZALASR extension
This is based on version v0.9 of the ZALASR specification [1].
The specification is listed as in Ratified state [2].
[1]: https://github.com/riscv/riscv-zalasr/tree/v0.9
[2]: https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Roan Richmond <roan.richmond@codethink.co.uk>
Message-ID: <20251112162923.311714-1-roan.richmond@codethink.co.uk>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d48ff50232..f22b504772 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -128,6 +128,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
+ ISA_EXT_DATA_ENTRY(zalasr, PRIV_VERSION_1_12_0, ext_zalasr),
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
@@ -1230,6 +1231,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zama16b", ext_zama16b, false),
MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false),
MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
+ MULTI_EXT_CFG_BOOL("zalasr", ext_zalasr, false),
MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 0a12ccd6cd..f4ff4f3f96 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -67,6 +67,7 @@ BOOL_FIELD(ext_zaamo)
BOOL_FIELD(ext_zacas)
BOOL_FIELD(ext_zama16b)
BOOL_FIELD(ext_zabha)
+BOOL_FIELD(ext_zalasr)
BOOL_FIELD(ext_zalrsc)
BOOL_FIELD(ext_zawrs)
BOOL_FIELD(ext_zfa)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b341832e41..6e35c4b1e6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1074,3 +1074,13 @@ amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st
amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st
+
+# *** Zalasr Standard Extension ***
+lb_aqrl 00110 . . ..... ..... 000 ..... 0101111 @atom_st
+lh_aqrl 00110 . . ..... ..... 001 ..... 0101111 @atom_st
+lw_aqrl 00110 . . ..... ..... 010 ..... 0101111 @atom_st
+ld_aqrl 00110 . . ..... ..... 011 ..... 0101111 @atom_st
+sb_aqrl 00111 . . ..... ..... 000 ..... 0101111 @atom_st
+sh_aqrl 00111 . . ..... ..... 001 ..... 0101111 @atom_st
+sw_aqrl 00111 . . ..... ..... 010 ..... 0101111 @atom_st
+sd_aqrl 00111 . . ..... ..... 011 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
new file mode 100644
index 0000000000..bf86805cef
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
@@ -0,0 +1,113 @@
+/*
+ * RISC-V translation routines for the ZALASR (Load-Aquire and Store-Release)
+ * Extension.
+ *
+ * Copyright (c) 2025 Roan Richmond, roan.richmond@codethink.co.uk
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * The documentation of the ISA extension can be found here:
+ * https://github.com/riscv/riscv-zalasr/tree/v0.9
+ */
+
+#define REQUIRE_ZALASR(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zalasr) { \
+ return false; \
+ } \
+} while (0)
+
+static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
+{
+ decode_save_opc(ctx, 0);
+
+ TCGv addr = get_address(ctx, a->rs1, 0);
+ TCGv dest = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGBar bar = (a->rl) ? TCG_BAR_STRL : 0;
+
+ /* Check that AQ is set, as this is mandatory */
+ if (!a->aq) {
+ return false;
+ }
+
+ memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
+
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ /* Add a memory barrier implied by AQ (mandatory) and RL (optional) */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ | bar);
+
+ return true;
+}
+
+static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
+{
+ REQUIRE_ZALASR(ctx);
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
+}
+
+static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
+{
+ REQUIRE_ZALASR(ctx);
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));
+}
+
+static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
+{
+ REQUIRE_ZALASR(ctx);
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZALASR(ctx);
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
+}
+
+static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
+{
+ decode_save_opc(ctx, 0);
+
+ TCGv addr = get_address(ctx, a->rs1, 0);
+ TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGBar bar = (a->aq) ? TCG_BAR_LDAQ : 0;
+
+ /* Check that RL is set, as this is mandatory */
+ if (!a->rl) {
+ return false;
+ }
+
+ memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
+
+ /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL | bar);
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
+ return true;
+}
+
+static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
+{
+ REQUIRE_ZALASR(ctx);
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
+}
+
+static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
+{
+ REQUIRE_ZALASR(ctx);
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));
+}
+
+static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
+{
+ REQUIRE_ZALASR(ctx);
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZALASR(ctx);
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 280ce48a1e..0d61420b46 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1199,6 +1199,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvzicond.c.inc"
#include "insn_trans/trans_rvzacas.c.inc"
#include "insn_trans/trans_rvzabha.c.inc"
+#include "insn_trans/trans_rvzalasr.c.inc"
#include "insn_trans/trans_rvzawrs.c.inc"
#include "insn_trans/trans_rvzicbo.c.inc"
#include "insn_trans/trans_rvzimop.c.inc"