Commit 3db74afec3 for qemu.org

commit 3db74afec3ca87f81fbdf5918ed1e21d837fbfab
Author: Alexandra Diupina <adiupina@astralinux.ru>
Date:   Mon Oct 14 17:05:51 2024 +0100

    hw/intc/arm_gicv3_cpuif: Add cast to match the documentation

    The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
    When cast to uint64_t (for further bitwise OR), the 32 most
    significant bits will be filled with 1s. However, the documentation
    states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.

    Add an explicit cast to match the documentation.

    Found by Linux Verification Center (linuxtesting.org) with SVACE.

    Cc: qemu-stable@nongnu.org
    Fixes: c3f21b065a ("hw/intc/arm_gicv3_cpuif: Support vLPIs")
    Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
    Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 89359db700..ea1d1b3455 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -793,7 +793,7 @@ static void icv_activate_vlpi(GICv3CPUState *cs)
     int regno = aprbit / 32;
     int regbit = aprbit % 32;

-    cs->ich_apr[cs->hppvlpi.grp][regno] |= (1 << regbit);
+    cs->ich_apr[cs->hppvlpi.grp][regno] |= (1U << regbit);
     gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0);
 }