Commit 4ee64205ffaa for kernel

commit 4ee64205ffaa587e8114d84a67ac721399ccb369
Merge: a85d6ff99411 6b701fde9b31
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Tue Apr 21 08:33:26 2026 -0700

    Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

    Pull clk updates from Stephen Boyd:
     "We've finally gotten rid of the struct clk_ops::round_rate() code
      after months of effort from Brian Masney. Now the only option is to
      use determine_rate(), which is good because that takes a struct
      argument instead of just a couple unsigned longs, allowing us to
      easily modify the way we determine and set rates in the clk tree.

      Beyond that core framework change we've got the typical pile of new
      SoC clk driver additions, fixes for clk data and/or adding missing
      clks because the consumer driver using those clks wasn't ready, etc.
      The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
      Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
      eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
      pretty normal.

      Core:
       - Remove the round_rate() clk op (yay!)

      New Drivers:
       - ESWIN eic700 SoC clk support
       - Econet EN751221 SoC clock/reset support
       - Global TCSR, RPMh, and display clock controller support for the
         Qualcomm Eliza platform
       - TCSR, the multiple global, and the RPMh clock controller support
         for the Qualcomm Nord platform
       - GPU clock controller support for Qualcomm SM8750
       - Video and GPU clock controller support for Qualcomm Glymur
       - Global clock controller support for Qualcomm IPQ5210
       - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
         controllers on the SoC
       - ExynosAutov920: Add G3D (GPU) clock controller
       - Clock driver for the Rockchip RV1103B SoC
       - Initial support for the Renesas RZ/G3L (R9A08G046) SoC
       - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
      clk: visconti: pll: initialize clk_init_data to zero
      clk: fsl-sai: Add MCLK generation support
      clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
      dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
      clk: fsl-sai: Add i.MX8M support with 8 byte register offset
      clk: fsl-sai: Sort the headers
      dt-bindings: clock: fsl-sai: Document i.MX8M support
      clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
      clk: qcom: rpmh: Add support for Nord rpmh clocks
      clk: qcom: Add TCSR clock driver for Nord SoC
      dt-bindings: clock: qcom: Add Nord Global Clock Controller
      dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
      dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
      clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
      clk: qcom: Constify list of critical CBCR registers
      clk: qcom: Constify qcom_cc_driver_data
      clk: qcom: videocc-glymur: Constify qcom_cc_desc
      clk: qcom: Add a driver for SM8750 GPU clocks
      dt-bindings: clock: qcom: Add SM8750 GPU clocks
      clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
      ...