Commit 4f53de2f10 for qemu.org
commit 4f53de2f103d6dfb5ad0498995d91a9694f40dd2
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: Mon Sep 1 12:08:05 2025 +0800
hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC
The ast2700-a1 SOC represented the first revision of the AST2700 and
was intended as an early engineering sample rather than a production
platform. A newer revision, A1, is now supported, and the ast2700-a1
SOC should replace the older A0 version.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 70be3871bb..6d6ffe3127 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -100,56 +100,6 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
#define AST2700_MAX_IRQ 256
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
-static const int aspeed_soc_ast2700a0_irqmap[] = {
- [ASPEED_DEV_SDMC] = 0,
- [ASPEED_DEV_HACE] = 4,
- [ASPEED_DEV_XDMA] = 5,
- [ASPEED_DEV_UART4] = 8,
- [ASPEED_DEV_SCU] = 12,
- [ASPEED_DEV_RTC] = 13,
- [ASPEED_DEV_EMMC] = 15,
- [ASPEED_DEV_TIMER1] = 16,
- [ASPEED_DEV_TIMER2] = 17,
- [ASPEED_DEV_TIMER3] = 18,
- [ASPEED_DEV_TIMER4] = 19,
- [ASPEED_DEV_TIMER5] = 20,
- [ASPEED_DEV_TIMER6] = 21,
- [ASPEED_DEV_TIMER7] = 22,
- [ASPEED_DEV_TIMER8] = 23,
- [ASPEED_DEV_DP] = 28,
- [ASPEED_DEV_EHCI1] = 33,
- [ASPEED_DEV_EHCI2] = 37,
- [ASPEED_DEV_LPC] = 128,
- [ASPEED_DEV_IBT] = 128,
- [ASPEED_DEV_KCS] = 128,
- [ASPEED_DEV_ADC] = 130,
- [ASPEED_DEV_GPIO] = 130,
- [ASPEED_DEV_SGPIOM0] = 130,
- [ASPEED_DEV_SGPIOM1] = 130,
- [ASPEED_DEV_I2C] = 130,
- [ASPEED_DEV_FMC] = 131,
- [ASPEED_DEV_WDT] = 131,
- [ASPEED_DEV_PWM] = 131,
- [ASPEED_DEV_I3C] = 131,
- [ASPEED_DEV_UART0] = 132,
- [ASPEED_DEV_UART1] = 132,
- [ASPEED_DEV_UART2] = 132,
- [ASPEED_DEV_UART3] = 132,
- [ASPEED_DEV_UART5] = 132,
- [ASPEED_DEV_UART6] = 132,
- [ASPEED_DEV_UART7] = 132,
- [ASPEED_DEV_UART8] = 132,
- [ASPEED_DEV_UART9] = 132,
- [ASPEED_DEV_UART10] = 132,
- [ASPEED_DEV_UART11] = 132,
- [ASPEED_DEV_UART12] = 132,
- [ASPEED_DEV_ETH1] = 132,
- [ASPEED_DEV_ETH2] = 132,
- [ASPEED_DEV_ETH3] = 132,
- [ASPEED_DEV_PECI] = 133,
- [ASPEED_DEV_SDHCI] = 133,
-};
-
static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_SDMC] = 0,
[ASPEED_DEV_HACE] = 4,
@@ -1069,35 +1019,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
AST2700_SOC_IOMEM_SIZE);
}
-static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data)
-{
- static const char * const valid_cpu_types[] = {
- ARM_CPU_TYPE_NAME("cortex-a35"),
- NULL
- };
- DeviceClass *dc = DEVICE_CLASS(oc);
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-
- /* Reason: The Aspeed SoC can only be instantiated from a board */
- dc->user_creatable = false;
- dc->realize = aspeed_soc_ast2700_realize;
-
- sc->valid_cpu_types = valid_cpu_types;
- sc->silicon_rev = AST2700_A0_SILICON_REV;
- sc->sram_size = 0x20000;
- sc->pcie_num = 0;
- sc->spis_num = 3;
- sc->sgpio_num = 2;
- sc->ehcis_num = 2;
- sc->wdts_num = 8;
- sc->macs_num = 1;
- sc->uarts_num = 13;
- sc->num_cpus = 4;
- sc->uarts_base = ASPEED_DEV_UART0;
- sc->irqmap = aspeed_soc_ast2700a0_irqmap;
- sc->memmap = aspeed_soc_ast2700_memmap;
-}
-
static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
{
static const char * const valid_cpu_types[] = {
@@ -1133,11 +1054,6 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
.parent = TYPE_ASPEED_SOC,
.instance_size = sizeof(Aspeed27x0SoCState),
.abstract = true,
- }, {
- .name = "ast2700-a0",
- .parent = TYPE_ASPEED27X0_SOC,
- .instance_init = aspeed_soc_ast2700_init,
- .class_init = aspeed_soc_ast2700a0_class_init,
},
{
.name = "ast2700-a1",