Commit 5801dc1b3b for qemu.org

commit 5801dc1b3bc5c7b20d4cdc1d464d99e55d3eea3f
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Wed Feb 18 18:40:14 2026 +0000

    target/arm: Handle SME-without-SVE on change of EL

    aarch64_sve_change_el() currently assumes that SME implies
    SVE, and will return without doing anything if SVE is not
    implemented, skipping a possible requirement to change
    the vector register state because the SME vector length
    has changed. Update it to handle SME also.

    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Message-id: 20260202133353.2231685-8-peter.maydell@linaro.org

diff --git a/target/arm/helper.c b/target/arm/helper.c
index ebf185000b..e12b2455d3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10139,8 +10139,8 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
     int old_len, new_len;
     bool old_a64, new_a64, sm;

-    /* Nothing to do if no SVE.  */
-    if (!cpu_isar_feature(aa64_sve, cpu)) {
+    /* Nothing to do if no SVE or SME.  */
+    if (!cpu_isar_feature(aa64_sve, cpu) && !cpu_isar_feature(aa64_sme, cpu)) {
         return;
     }