Commit 5dcc64828d for qemu.org

commit 5dcc64828dc79c2426905db5fae885f6ccf93347
Author: Alistair Francis <alistair.francis@wdc.com>
Date:   Thu Apr 16 09:37:40 2026 +1000

    target/riscv: Use ELEN for Fractional LMUL check

    The RISC-V spec states that

    """
    For a given supported fractional LMUL setting, implementations
    must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
    """

    We were previously checking VLEN, instead of ELEN, so let's update to
    check ELEN instead of VLEN for fractional scaling.

    Cc: qemu-stable@nongnu.org
    Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
    Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
    Reviewed-by: Max Chou <max.chou@sifive.com>
    Message-ID: <20260415233740.3027321-5-alistair.francis@wdc.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 538168efc9..5a3554dd71 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -70,18 +70,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     bool ill_altfmt = true;
     int xlen = riscv_cpu_xlen(env);
     bool vill = (s2 >> (xlen - 1)) & 0x1;
-    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;

     if (vlmul & 4) {
         /*
          * Fractional LMUL, check:
          *
-         * VLEN * LMUL >= SEW
-         * VLEN >> (8 - lmul) >= sew
-         * (vlenb << 3) >> (8 - lmul) >= sew
+         * ELEN * LMUL >= SEW
+         * ELEN >> (8 - vlmul) >= sew
          */
-        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
+        if (vlmul == 4 ||
+            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
             vill = true;
         }
     }