Commit 7228d61b11 for qemu.org

commit 7228d61b110da94b50bccd98835523831b7e4b1f
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Tue May 12 10:38:55 2026 +0100

    hw/intc/arm_gicv5: Avoid NULL dereference in trace line

    In the handling of writes to the IRS_SPI_RESAMPLER register,
    we call a trace function, passing it information about the SPI
    being resampled. However, spi could be NULL if the guest tried
    to resample a nonexistent SPI or one configured for a different
    domain. Move the trace statement inside the "if (spi)" block,
    as it's only interesting trace if we actually did a resample
    and potentially changed the state of the SPI.

    CID: 1959593
    Fixes: 33185e1d64e ("hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events")
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Message-id: 20260512093856.3197700-4-peter.maydell@linaro.org

diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
index 493d664625..7ad274e369 100644
--- a/hw/intc/arm_gicv5.c
+++ b/hw/intc/arm_gicv5.c
@@ -1643,8 +1643,8 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,
         if (spi) {
             spi_sample(spi);
             irs_recalc_hppi(s, spi->domain, spi->iaffid);
+            trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active);
         }
-        trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active);
         return true;
     }
     case A_IRS_CR0: