Commit 73fa4597bdc0 for kernel

commit 73fa4597bdc035437fbcd84d6be32bd39f1f2149
Author: Alexis Lothore <alexis.lothore@bootlin.com>
Date:   Wed Apr 23 09:12:09 2025 +0200

    net: stmmac: fix dwmac1000 ptp timestamp status offset

    When a PTP interrupt occurs, the driver accesses the wrong offset to
    learn about the number of available snapshots in the FIFO for dwmac1000:
    it should be accessing bits 29..25, while it is currently reading bits
    19..16 (those are bits about the auxiliary triggers which have generated
    the timestamps). As a consequence, it does not compute correctly the
    number of available snapshots, and so possibly do not generate the
    corresponding clock events if the bogus value ends up being 0.

    Fix clock events generation by reading the correct bits in the timestamp
    register for dwmac1000.

    Fixes: 477c3e1f6363 ("net: stmmac: Introduce dwmac1000 timestamping operations")
    Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
    Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
    Link: https://patch.msgid.link/20250423-stmmac_ts-v2-1-e2cf2bbd61b1@bootlin.com
    Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index 967a16212faf..0c011a47d5a3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -320,8 +320,8 @@ enum rtc_control {

 /* PTP and timestamping registers */

-#define GMAC3_X_ATSNS       GENMASK(19, 16)
-#define GMAC3_X_ATSNS_SHIFT 16
+#define GMAC3_X_ATSNS       GENMASK(29, 25)
+#define GMAC3_X_ATSNS_SHIFT 25

 #define GMAC_PTP_TCR_ATSFC	BIT(24)
 #define GMAC_PTP_TCR_ATSEN0	BIT(25)