Commit 8e35971a56 for qemu.org

commit 8e35971a561bdbaa8948f6cb32023d3de88e821d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date:   Mon Jun 23 14:21:18 2025 -0300

    target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()

    We're missing fflags and frm.

    Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-ID: <20250623172119.997166-3-dbarboza@ventanamicro.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c22c418625..063374be62 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -594,6 +594,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         }
     }
     if (flags & CPU_DUMP_FPU) {
+        riscv_dump_csr(env, CSR_FFLAGS, f);
+        riscv_dump_csr(env, CSR_FRM, f);
         riscv_dump_csr(env, CSR_FCSR, f);

         for (i = 0; i < 32; i++) {