Commit 8ed21f4ba6 for qemu.org

commit 8ed21f4ba6135a54aa8534f40874d90d1f9e9602
Author: Kane Chen <kane_chen@aspeedtech.com>
Date:   Wed Feb 4 08:21:17 2026 +0000

    hw/arm/aspeed: Attach LTPI controller to AST27X0 platform

    Connect the LTPI controller device (representing the AST1700 I/O
    expander) to the AST27X0 SoC model. This patch sets up the memory
    mapping and device registration according to the AST2700 SoC design,
    where the LTPI controller is exposed at fixed MMIO regions.

    This change only handles device instantiation and integration,
    without implementing the controller's internal logic.

    Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
    Reviewed-by: Cédric Le Goater <clg@redhat.com>
    Reviewed-by: Nabih Estefan <nabihestefan@google.com>
    Tested-by: Nabih Estefan <nabihestefan@google.com>
    Link: https://lore.kernel.org/qemu-devel/20260204082113.3955407-3-kane_chen@aspeedtech.com
    Signed-off-by: Cédric Le Goater <clg@redhat.com>

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index e16183c3b3..bbcb6e0127 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -88,6 +88,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
     [ASPEED_DEV_UART10]    =  0x14C33900,
     [ASPEED_DEV_UART11]    =  0x14C33A00,
     [ASPEED_DEV_UART12]    =  0x14C33B00,
+    [ASPEED_DEV_LTPI_CTRL1] =  0x14C34000,
+    [ASPEED_DEV_LTPI_CTRL2] =  0x14C35000,
     [ASPEED_DEV_WDT]       =  0x14C37000,
     [ASPEED_DEV_LTPI]      =  0x30000000,
     [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
@@ -491,6 +493,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
         object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
     }

+    for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
+        object_initialize_child(obj, "ltpi-ctrl[*]",
+                                &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
+    }
+
     object_initialize_child(obj, "dpmcu", &s->dpmcu,
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "ltpi", &s->ltpi,
@@ -974,6 +981,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
         return;
     }

+    /* LTPI controller */
+    for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
+        AspeedLTPIState *ltpi_ctrl;
+        hwaddr ltpi_base;
+
+        ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
+        ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
+
+        if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
+            return;
+        }
+        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
+    }
+
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
                                   "aspeed.dpmcu",
                                   sc->memmap[ASPEED_DEV_DPMCU],
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 18ff961a38..bca10c387b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -43,6 +43,7 @@
 #include "hw/fsi/aspeed_apb2opb.h"
 #include "hw/char/serial-mm.h"
 #include "hw/intc/arm_gicv3.h"
+#include "hw/misc/aspeed_ltpi.h"

 #define VBOOTROM_FILE_NAME  "ast27x0_bootrom.bin"

@@ -55,6 +56,7 @@
 #define ASPEED_UARTS_NUM 13
 #define ASPEED_JTAG_NUM  2
 #define ASPEED_PCIE_NUM  3
+#define ASPEED_IOEXP_NUM 2

 struct AspeedSoCState {
     DeviceState parent;
@@ -112,6 +114,7 @@ struct AspeedSoCState {
     UnimplementedDeviceState ltpi;
     UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
     AspeedAPB2OPBState fsi[2];
+    AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
 };

 #define TYPE_ASPEED_SOC "aspeed-soc"
@@ -279,6 +282,8 @@ enum {
     ASPEED_GIC_REDIST,
     ASPEED_DEV_IPC0,
     ASPEED_DEV_IPC1,
+    ASPEED_DEV_LTPI_CTRL1,
+    ASPEED_DEV_LTPI_CTRL2,
 };

 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);