Commit 978301bc33 for qemu.org
commit 978301bc33e3f662a072020848bfaaa08e01a0bf
Author: Sairaj Kodilkar <sarunkod@amd.com>
Date: Fri Aug 7 11:42:48 2026 +0530
acpi_build: Build IVRS feature report using extended feature register
Currently IVRS feature report values are hardcoded, this is difficult to
maintain as any updates to extended feature must be synced. Along with
it, current feature report does not have GATS and HATS set. Hence use
the extended feature registers to build the IVRS feature report.
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20260807061250.27739-6-sarunkod@amd.com>
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index a28bb2ec63..7bf3858b63 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1842,6 +1842,37 @@ ivrs_host_bridges(Object *obj, void *opaque)
return 0;
}
+/*
+ * IVHD type 0x10 reports features using Feature Reporting field, which has
+ * different format than extended feature register (EFR) in the IOMMU MMIO
+ * space.
+ *
+ * Convert the EFR format to feature reporting format.
+ */
+static uint32_t
+get_amd_ivhd_feature_report(uint64_t extended_feature)
+{
+ uint32_t feature_report;
+ uint64_t hats_mode = (extended_feature & AMDVI_HATS_MODE_MASK) >>
+ AMDVI_HATS_MODE_SHIFT;
+ uint64_t gats_mode = (extended_feature & AMDVI_GATS_MODE_MASK) >>
+ AMDVI_GATS_MODE_SHIFT;
+ uint32_t is_ia = !!(extended_feature & AMDVI_FEATURE_IA);
+ uint32_t is_ga = !!(extended_feature & AMDVI_FEATURE_GA);
+ uint32_t is_gt = !!(extended_feature & AMDVI_FEATURE_GT);
+ uint32_t is_xt = !!(extended_feature & AMDVI_FEATURE_XT);
+
+ feature_report =
+ hats_mode << AMDVI_IVHD_FEATURE_REPORT_HATS_SHIFT | /* HATS[31:30] */
+ gats_mode << AMDVI_IVHD_FEATURE_REPORT_GATS_SHIFT | /* GATS[29:28] */
+ is_ia << AMDVI_IVHD_FEATURE_REPORT_IA_SUP_SHIFT | /* IASup[5] */
+ is_ga << AMDVI_IVHD_FEATURE_REPORT_GA_SUP_SHIFT | /* GASup[6] */
+ is_gt << AMDVI_IVHD_FEATURE_REPORT_GT_SUP_SHIFT | /* GTSup[2] */
+ is_xt << AMDVI_IVHD_FEATURE_REPORT_XT_SUP_SHIFT; /* XTSup[0] */
+
+ return feature_report;
+}
+
static void
build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
const char *oem_table_id)
@@ -1850,8 +1881,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
GArray *ivhd_blob = g_array_new(false, true, 1);
AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
.oem_table_id = oem_table_id };
- uint64_t feature_report;
uint16_t iommu_devid = pci_get_bdf(&s->pci->dev);
+ uint64_t extended_feature = amdvi_extended_feature_register(s);
acpi_table_begin(&table, table_data);
/* IVinfo - IO virtualization information common to all
@@ -1924,14 +1955,9 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
/* IOMMU info */
build_append_int_noprefix(table_data, 0, 2);
/* IOMMU Feature Reporting */
- feature_report = (48UL << 30) | /* HATS */
- (48UL << 28) | /* GATS */
- (1UL << 2) | /* GTSup */
- (1UL << 6); /* GASup */
- if (s->xtsup) {
- feature_report |= (1UL << 0); /* XTSup */
- }
- build_append_int_noprefix(table_data, feature_report, 4);
+ build_append_int_noprefix(table_data,
+ get_amd_ivhd_feature_report(extended_feature),
+ 4);
/* IVHD entries as found above */
g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
@@ -1964,9 +1990,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
build_append_int_noprefix(table_data, 0, 4);
}
/* EFR Register Image */
- build_append_int_noprefix(table_data,
- amdvi_extended_feature_register(s),
- 8);
+ build_append_int_noprefix(table_data, extended_feature, 8);
/* EFR Register Image 2 */
build_append_int_noprefix(table_data, 0, 8);
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index d01f9b41df..319db18618 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -174,7 +174,11 @@
#define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, 48))
/* AMDVI paging mode */
+#define AMDVI_GATS_MODE_SHIFT (12)
+#define AMDVI_GATS_MODE_MASK (3ULL << 12)
#define AMDVI_GATS_MODE (2ULL << 12)
+#define AMDVI_HATS_MODE_SHIFT (10)
+#define AMDVI_HATS_MODE_MASK (3ULL << 10)
#define AMDVI_HATS_MODE (2ULL << 10)
#define AMDVI_HATS_MODE_RESERVED (3ULL << 10)
@@ -296,6 +300,13 @@
#define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62)
#define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63)
+#define AMDVI_IVHD_FEATURE_REPORT_HATS_SHIFT (30)
+#define AMDVI_IVHD_FEATURE_REPORT_GATS_SHIFT (28)
+#define AMDVI_IVHD_FEATURE_REPORT_GA_SUP_SHIFT (6)
+#define AMDVI_IVHD_FEATURE_REPORT_IA_SUP_SHIFT (5)
+#define AMDVI_IVHD_FEATURE_REPORT_GT_SUP_SHIFT (2)
+#define AMDVI_IVHD_FEATURE_REPORT_XT_SUP_SHIFT (0)
+
#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE)