Commit 9869b871eb for qemu.org

commit 9869b871eb52f97171a74613d052c8cce6d9a04d
Author: Jay Chang <jay.chang@sifive.com>
Date:   Mon May 18 15:22:39 2026 +0800

    hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

    Align SPEC: Bare mode contexts are not cached, so they require
    direct memory deallocation via g_free instead of hash table cleanup.

    Signed-off-by: Jay Chang <jay.chang@sifive.com>
    Reviewed-by: Frank Chang <frank.chang@sifive.com>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
    Message-ID: <20260518072239.16293-3-jay.chang@sifive.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 5b28b1ad63..a500cb8440 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1390,7 +1390,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,

 static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref)
 {
-    if (ref) {
+    unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
+
+    if (!ref) {
+        return;
+    }
+
+    /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */
+    if (mode == RISCV_IOMMU_DDTP_MODE_BARE) {
+        g_free(ref);
+    } else {
         g_hash_table_unref((GHashTable *)ref);
     }
 }