Commit a59157f98f for qemu.org

commit a59157f98f0b69b0bbdb26bc15fbc4d6c8060799
Merge: 8241394f7e 64ce9ac187
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date:   Thu Jul 2 10:44:50 2026 +0200

    Merge tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.1

    * Fix IMSIC CSR write and add tests
    * Parametrise debug trigger number
    * Add 'svbare' satp-mode
    * Fix RINTC PLIC context ID for KVM
    * Avoid abort when reading vtype before env->xl is set
    * Skip reset for KVM irqchip
    * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE
    * More FDT cleanups (PLIC)
    * Make FCTL.BE in IOMMU read only 0
    * Check DC.TC reserved bits in IOMMU
    * Apply UXL WARL handling to vsstatus
    * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU
    * Set RISCV_IOMMU_FQ_HDR_PV appropriately
    * Fix MSI MRIF IOMMU interrupt-pending offset
    * Report QEMU CPU archid as 42
    * Check PMP before updating PTE
    * Add the Tenstorrent Atlantis machine

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    * tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu: (39 commits)
      hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0
      hw/riscv/atlantis: Add some i2c peripherals
      hw/riscv/atlantis: Integrate i2c controllers
      hw/i2c: Add DesignWare I2C Controller
      tests/functional/riscv64: Add tt-atlantis tests
      hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr
      hw/riscv: Add Tenstorrent Atlantis machine
      target/riscv: tt-ascalon: Enable Zkr extension
      hw/riscv/aia: Configure stride for the M-mode IMSIC
      hw/riscv/aia: Provide number of irq sources
      hw/riscv/virt: Move AIA initialisation to helper file
      hw/riscv/boot: Account for discontiguous memory when loading firmware
      hw/riscv/boot: Describe discontiguous memory in boot_info
      target/riscv: Check PMP before updating PTE
      target/riscv: Report QEMU CPU archid as 42
      hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset
      hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately
      hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set
      target/riscv: Apply UXL WARL handling to vsstatus
      hw/riscv/riscv-iommu: check DC.TC reserved bits
      ...

    Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>