Commit a61288200e8b for kernel

commit a61288200e8b6f42bff116508dc72ebcc206f10a
Merge: 49219bba0149 5c4663ed1eac
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Tue Dec 2 11:04:37 2025 -0800

    Merge tag 'ras_core_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

    Pull x86 RAS updates from Borislav Petkov:

     - The second part of the AMD MCA interrupts rework after the
       last-minute show-stopper from the last merge window was sorted out.
       After this, the AMD MCA deferred errors, thresholding and corrected
       errors interrupt handlers use common MCA code and are tightly
       integrated into the core MCA code, thereby getting rid of
       considerable duplication. All culminating into allowing CMCI error
       thresholding storms to be detected at AMD too, using the common
       infrastructure

     - Add support for two new MCA bank bits on AMD Zen6 which denote
       whether the error address logged is a system physical address, which
       obviates the need for it to be translated before further error
       recovery can be done

    * tag 'ras_core_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
      x86/mce: Handle AMD threshold interrupt storms
      x86/mce: Do not clear bank's poll bit in mce_poll_banks on AMD SMCA systems
      x86/mce: Add support for physical address valid bit
      x86/mce: Save and use APEI corrected threshold limit
      x86/mce/amd: Define threshold restart function for banks
      x86/mce/amd: Remove redundant reset_block()
      x86/mce/amd: Support SMCA Corrected Error Interrupt
      x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
      x86/mce: Unify AMD DFR handler with MCA Polling
      x86/mce: Unify AMD THR handler with MCA Polling