Commit b675697d8075 for kernel

commit b675697d807507244bfd00adc30534df6e888cfd
Merge: 16c3c4e2881e d8b210f87292 d5798ed98baa 448b50b5cf12 847eaf0d3123
Author: Stephen Boyd <sboyd@kernel.org>
Date:   Sat Feb 14 10:23:37 2026 -0800

    Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next

    * clk-amlogic:
      clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
      clk: meson: g12a: Limit the HDMI PLL OD to /4
      clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
      clk: amlogic: remove potentially unsafe flags from S4 video clocks
      clk: amlogic: add video-related clocks for S4 SoC
      dt-bindings: clock: add video clock indices for Amlogic S4 SoC
      clk: meson: t7: add t7 clock peripherals controller driver
      clk: meson: t7: add support for the T7 SoC PLL clock
      dt-bindings: clock: add Amlogic T7 peripherals clock controller
      dt-bindings: clock: add Amlogic T7 SCMI clock controller
      dt-bindings: clock: add Amlogic T7 PLL clock controller

    * clk-thead:
      clk: thead: th1520-ap: Support CPU frequency scaling
      clk: thead: th1520-ap: Add macro to define multiplexers with flags
      clk: thead: th1520-ap: Support setting PLL rates
      clk: thead: th1520-ap: Add C910 bus clock
      clk: thead: th1520-ap: Poll for PLL lock and wait for stability
      dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock

    * clk-mediatek:
      Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
      clk: mediatek: Fix error handling in runtime PM setup
      clk: mediatek: don't select clk-mt8192 for all ARM64 builds
      clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
      clk: mediatek: Refactor pllfh registration to pass device
      clk: mediatek: Pass device to clk_hw_register for PLLs
      clk: mediatek: Refactor pll registration to pass device
      clk: Respect CLK_OPS_PARENT_ENABLE during recalc
      dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible
      clk: mediatek: Drop __initconst from gates

    * clk-samsung:
      clk: samsung: gs101: add support for Display Process Unit (DPU) clocks
      dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
      dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
      dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
      clk: samsung: fix sysreg save/restore when PM is enabled for CMU
      clk: samsung: avoid warning message on legacy Exynos (auto clock gating)
      clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU
      clk: samsung: Implement automatic clock gating mode for CMUs
      dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required
      clk: samsung: exynosautov920: add clock support
      dt-bindings: clock: exynosautov920: add MFD clock definitions