Commit c38e9dc3b6 for qemu.org

commit c38e9dc3b6e27e738f50920b02a8dd0c90a061ef
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Wed Feb 18 18:40:14 2026 +0000

    target/arm: Squash FEAT_SME_FA64 if FEAT_SVE is not present

    FEAT_SME_FA64 allows Streaming SVE code to access the whole
    SVE instruction set; it requires FEAT_SVE to be present. If
    we have a CPU with SME but not SVE, squash the FA64 bit in
    arm_cpu_sme_finalize().

    This doesn't have any effect at the moment because we don't
    let the user create an SME-without-SVE CPU, but we are about
    to lift that restriction.

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260202133353.2231685-15-peter.maydell@linaro.org

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index b2be8c9fba..dec430c48b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -388,6 +388,11 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
         /* SME2 or better */
         FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2);
     }
+
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        /* FEAT_SME_FA64 requires SVE, not just SME */
+        FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, 0);
+    }
 }

 static bool cpu_arm_get_sme(Object *obj, Error **errp)