Commit cacd346296 for qemu.org
commit cacd3462963a0a4f5bab4263ce79c2aa4b32692d
Merge: 46fb70f8a1 dfad6f9ff1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: Sun Sep 6 15:13:29 2026 +0100
Merge tag 'pull-hex-20260905' of https://github.com/qualcomm/qemu into staging
hexagon: TLB, badva fixes + DMA
Add fixes for TLB, badva behavior and an unimp placeholder for the
DMA instruction set.
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# gpg: Signature made Sat Sep 5 21:05:19 2026 BST
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [full]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [full]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [full]
# gpg: aka "bcain" [full]
# gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20260905' of https://github.com/qualcomm/qemu:
target/hexagon: decode the DMA insts as unimp
tests/functional/hexagon: update arch tests to v0.2.14
tests/functional/hexagon: add tests, update to v0.2.14
hexagon: raise imprecise exception for multi-TLB matches
target/hexagon: assert guest register pair alignment
hw/intc: name the L2VIC edge trigger check
target/hexagon: kick vCPU when re-asserting interrupts
target/hexagon: read BADVA as an alias of BADVA0/1
hw/hexagon: register the V68N_1024 machine
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>