Commit cee73b1e840c for kernel
commit cee73b1e840c154f64ace682cb477c1ae2e29cc4
Merge: 7563f7e0e9fc 18be4ca5cb4e
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Thu Feb 12 19:17:44 2026 -0800
Merge tag 'riscv-for-linus-7.0-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley:
- Add support for control flow integrity for userspace processes.
This is based on the standard RISC-V ISA extensions Zicfiss and
Zicfilp
- Improve ptrace behavior regarding vector registers, and add some
selftests
- Optimize our strlen() assembly
- Enable the ISO-8859-1 code page as built-in, similar to ARM64, for
EFI volume mounting
- Clean up some code slightly, including defining copy_user_page() as
copy_page() rather than memcpy(), aligning us with other
architectures; and using max3() to slightly simplify an expression
in riscv_iommu_init_check()
* tag 'riscv-for-linus-7.0-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
riscv: lib: optimize strlen loop efficiency
selftests: riscv: vstate_exec_nolibc: Use the regular prctl() function
selftests: riscv: verify ptrace accepts valid vector csr values
selftests: riscv: verify ptrace rejects invalid vector csr inputs
selftests: riscv: verify syscalls discard vector context
selftests: riscv: verify initial vector state with ptrace
selftests: riscv: test ptrace vector interface
riscv: ptrace: validate input vector csr registers
riscv: csr: define vtype register elements
riscv: vector: init vector context with proper vlenb
riscv: ptrace: return ENODATA for inactive vector extension
kselftest/riscv: add kselftest for user mode CFI
riscv: add documentation for shadow stack
riscv: add documentation for landing pad / indirect branch tracking
riscv: create a Kconfig fragment for shadow stack and landing pad support
arch/riscv: add dual vdso creation logic and select vdso based on hw
arch/riscv: compile vdso with landing pad and shadow stack note
riscv: enable kernel access to shadow stack memory via the FWFT SBI call
riscv: add kernel command line option to opt out of user CFI
riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe
...
diff --cc Documentation/arch/riscv/index.rst
index 830fde0c8aa3,e240eb0ceb70..ac535c52d509
--- a/Documentation/arch/riscv/index.rst
+++ b/Documentation/arch/riscv/index.rst
@@@ -14,5 -14,14 +14,7 @@@ RISC-V architectur
uabi
vector
cmodx
+ zicfilp
+ zicfiss
features
-
-.. only:: subproject and html
-
- Indices
- =======
-
- * :ref:`genindex`
diff --cc arch/riscv/include/asm/page.h
index 061b60b954ec,3c517bc9eac5..187aad0a7b03
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@@ -50,8 -50,8 +50,7 @@@ void clear_page(void *page)
#endif
#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)
- #define copy_user_page(vto, vfrom, vaddr, topg) \
- memcpy((vto), (vfrom), PAGE_SIZE)
-#define clear_user_page(pgaddr, vaddr, page) clear_page(pgaddr)
+ #define copy_user_page(vto, vfrom, vaddr, topg) copy_page(vto, vfrom)
/*
* Use struct definitions to apply C type checking
diff --cc include/uapi/linux/prctl.h
index 79944b7ae50a,f57098fb0ba8..55b0446fff9d
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@@ -386,14 -386,31 +386,41 @@@ struct prctl_mm_map
# define PR_FUTEX_HASH_SET_SLOTS 1
# define PR_FUTEX_HASH_GET_SLOTS 2
+/* RSEQ time slice extensions */
+#define PR_RSEQ_SLICE_EXTENSION 79
+# define PR_RSEQ_SLICE_EXTENSION_GET 1
+# define PR_RSEQ_SLICE_EXTENSION_SET 2
+/*
+ * Bits for RSEQ_SLICE_EXTENSION_GET/SET
+ * PR_RSEQ_SLICE_EXT_ENABLE: Enable
+ */
+# define PR_RSEQ_SLICE_EXT_ENABLE 0x01
+
+ /*
+ * Get the current indirect branch tracking configuration for the current
+ * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
+ */
-#define PR_GET_INDIR_BR_LP_STATUS 79
++#define PR_GET_INDIR_BR_LP_STATUS 80
+
+ /*
+ * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
+ * enable cpu feature for user thread, to track all indirect branches and ensure
+ * they land on arch defined landing pad instruction.
+ * x86 - If enabled, an indirect branch must land on an ENDBRANCH instruction.
+ * arch64 - If enabled, an indirect branch must land on a BTI instruction.
+ * riscv - If enabled, an indirect branch must land on an lpad instruction.
+ * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
+ * branches will no more be tracked by cpu to land on arch defined landing pad
+ * instruction.
+ */
-#define PR_SET_INDIR_BR_LP_STATUS 80
++#define PR_SET_INDIR_BR_LP_STATUS 81
+ # define PR_INDIR_BR_LP_ENABLE (1UL << 0)
+
+ /*
+ * Prevent further changes to the specified indirect branch tracking
+ * configuration. All bits may be locked via this call, including
+ * undefined bits.
+ */
-#define PR_LOCK_INDIR_BR_LP_STATUS 81
++#define PR_LOCK_INDIR_BR_LP_STATUS 82
+
#endif /* _LINUX_PRCTL_H */
diff --cc kernel/sys.c
index 35ea9d79a42e,9071422c1609..c86eba9aa7e9
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@@ -2868,11 -2883,21 +2883,26 @@@ SYSCALL_DEFINE5(prctl, int, option, uns
case PR_FUTEX_HASH:
error = futex_hash_prctl(arg2, arg3, arg4);
break;
+ case PR_RSEQ_SLICE_EXTENSION:
+ if (arg4 || arg5)
+ return -EINVAL;
+ error = rseq_slice_extension_prctl(arg2, arg3);
+ break;
+ case PR_GET_INDIR_BR_LP_STATUS:
+ if (arg3 || arg4 || arg5)
+ return -EINVAL;
+ error = arch_get_indir_br_lp_status(me, (unsigned long __user *)arg2);
+ break;
+ case PR_SET_INDIR_BR_LP_STATUS:
+ if (arg3 || arg4 || arg5)
+ return -EINVAL;
+ error = arch_set_indir_br_lp_status(me, arg2);
+ break;
+ case PR_LOCK_INDIR_BR_LP_STATUS:
+ if (arg3 || arg4 || arg5)
+ return -EINVAL;
+ error = arch_lock_indir_br_lp_status(me, arg2);
+ break;
default:
trace_task_prctl_unknown(option, arg2, arg3, arg4, arg5);
error = -EINVAL;