Commit d5338d146e for qemu.org

commit d5338d146ef0ab8461efe9397151810c057de8c7
Author: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Date:   Wed Mar 11 11:59:17 2026 +0000

    target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks

    Add the RISC-V privileged ISA defined bit positions for the Supervisor
    Big-Endian (SBE, bit 36) and Machine Big-Endian (MBE, bit 37) fields
    in the mstatus register. These are used alongside the existing
    MSTATUS_UBE (bit 6) to control data endianness at each privilege level.

    The MSTATUS_UBE definition was already present, but SBE and MBE were
    missing.

    Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-ID: <20260527083151.17876-2-djordje.todorovic@htecgroup.com>
    Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b62dd82fe7..3f146a43fe 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -629,6 +629,8 @@
 #define MSTATUS_SPELP       0x00800000 /* zicfilp */
 #define MSTATUS_SDT         0x01000000
 #define MSTATUS_MPELP       0x020000000000 /* zicfilp */
+#define MSTATUS_SBE         0x1000000000ULL
+#define MSTATUS_MBE         0x2000000000ULL
 #define MSTATUS_GVA         0x4000000000ULL
 #define MSTATUS_MPV         0x8000000000ULL
 #define MSTATUS_MDT         0x40000000000ULL /* Smdbltrp extension */