Commit db19ef221f for qemu.org
commit db19ef221f241ae35be0887ec05b36b69e4a647c
Author: Jithu Joseph <jithu.joseph@oss.qualcomm.com>
Date: Thu Jun 4 07:22:05 2026 -0700
hw/i3c: rename DW-I3C queue capacity fields from _bytes to _words
The cmd/resp, tx/rx, and IBI queue capacity values are passed straight
to fifo32_create(), which interprets its capacity argument as a 32-bit
word count. The fields and device properties were therefore misnamed:
setting e.g. tx-rx-queue-capacity-bytes=N sized the backing FIFO to N
words, not N bytes.
Rename the three struct fields and matching device-property strings:
cmd_resp_queue_capacity_bytes -> cmd_resp_queue_capacity_words
tx_rx_queue_capacity_bytes -> tx_rx_queue_capacity_words
ibi_queue_capacity_bytes -> ibi_queue_capacity_words
Defaults are unchanged (0x10 / 0x40 / 0x10) -- they were being
interpreted as word counts by fifo32_create() all along, just under a
misleading label. No behavioral change.
Signed-off-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260604142207.2118098-3-jithu.joseph@oss.qualcomm.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index 06c2d55f59..0d32d9ce78 100644
--- a/hw/i3c/dw-i3c.c
+++ b/hw/i3c/dw-i3c.c
@@ -948,9 +948,9 @@ static void dw_i3c_reset(DeviceState *dev)
ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,
s->cfg.dev_char_table_depth);
ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
- s->cfg.cmd_resp_queue_capacity_bytes);
+ s->cfg.cmd_resp_queue_capacity_words);
ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
- s->cfg.tx_rx_queue_capacity_bytes);
+ s->cfg.tx_rx_queue_capacity_words);
dw_i3c_cmd_queue_reset(s);
dw_i3c_resp_queue_reset(s);
@@ -1798,9 +1798,9 @@ static void dw_i3c_reset_enter(Object *obj, ResetType type)
ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,
s->cfg.dev_char_table_depth);
ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
- s->cfg.cmd_resp_queue_capacity_bytes);
+ s->cfg.cmd_resp_queue_capacity_words);
ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
- s->cfg.tx_rx_queue_capacity_bytes);
+ s->cfg.tx_rx_queue_capacity_words);
}
static void dw_i3c_realize(DeviceState *dev, Error **errp)
@@ -1814,14 +1814,14 @@ static void dw_i3c_realize(DeviceState *dev, Error **errp)
DW_I3C_NR_REGS << 2);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);
- fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_bytes);
- fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_bytes);
- fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_bytes);
- fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_bytes);
- fifo32_create(&s->ibi_queue, s->cfg.ibi_queue_capacity_bytes);
+ fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_words);
+ fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_words);
+ fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_words);
+ fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_words);
+ fifo32_create(&s->ibi_queue, s->cfg.ibi_queue_capacity_words);
/* Arbitrarily large enough to not be an issue. */
fifo8_create(&s->ibi_data.ibi_intermediate_queue,
- s->cfg.ibi_queue_capacity_bytes * 8);
+ s->cfg.ibi_queue_capacity_words * 8);
s->bus = i3c_init_bus(DEVICE(s), name);
I3CBusClass *bc = I3C_BUS_GET_CLASS(s->bus);
@@ -1832,12 +1832,12 @@ static void dw_i3c_realize(DeviceState *dev, Error **errp)
static const Property dw_i3c_properties[] = {
DEFINE_PROP_UINT8("device-id", DWI3C, cfg.id, 0),
- DEFINE_PROP_UINT8("command-response-queue-capacity-bytes", DWI3C,
- cfg.cmd_resp_queue_capacity_bytes, 0x10),
- DEFINE_PROP_UINT16("tx-rx-queue-capacity-bytes", DWI3C,
- cfg.tx_rx_queue_capacity_bytes, 0x40),
- DEFINE_PROP_UINT8("ibi-queue-capacity-bytes", DWI3C,
- cfg.ibi_queue_capacity_bytes, 0x10),
+ DEFINE_PROP_UINT8("command-response-queue-capacity-words", DWI3C,
+ cfg.cmd_resp_queue_capacity_words, 0x10),
+ DEFINE_PROP_UINT16("tx-rx-queue-capacity-words", DWI3C,
+ cfg.tx_rx_queue_capacity_words, 0x40),
+ DEFINE_PROP_UINT8("ibi-queue-capacity-words", DWI3C,
+ cfg.ibi_queue_capacity_words, 0x10),
DEFINE_PROP_UINT8("num-addressable-devices", DWI3C,
cfg.num_addressable_devices, 8),
DEFINE_PROP_UINT16("dev-addr-table-pointer", DWI3C,
diff --git a/include/hw/i3c/dw-i3c.h b/include/hw/i3c/dw-i3c.h
index d26f60580f..391470207c 100644
--- a/include/hw/i3c/dw-i3c.h
+++ b/include/hw/i3c/dw-i3c.h
@@ -181,9 +181,9 @@ struct DWI3C {
struct {
uint8_t id;
- uint8_t cmd_resp_queue_capacity_bytes;
- uint16_t tx_rx_queue_capacity_bytes;
- uint8_t ibi_queue_capacity_bytes;
+ uint8_t cmd_resp_queue_capacity_words;
+ uint16_t tx_rx_queue_capacity_words;
+ uint8_t ibi_queue_capacity_words;
uint8_t num_addressable_devices;
uint16_t dev_addr_table_pointer;
uint16_t dev_addr_table_depth;