Commit dc634aa347 for qemu.org

commit dc634aa347abcdbd9eca54d2a6c93f5b1b200ff6
Author: Joel Stanley <joel@jms.id.au>
Date:   Wed Jan 14 12:35:15 2026 +1030

    target/riscv: tt-ascalon: Add Tenstorrent mvendorid

    JEP106 has two vendor IDs for Tenstorrent. We will use Bank 16, company 33:

      ((16 - 1) << 7) | 33 = 0x7a1

    As JEP106 requires registration to download, the number can confirmed by
    looking at the OpenOCD sources[1].

    Alternatively, referring to the JEDEC document the hex IDs are listed with the
    parity (MSB) bit added. Company 33 has hex 0xa1:

     ((16 - 1) << 7) | (0xa1 & ~0x80) = 0x7a1

    Add it to the Ascalon CPU definition as the mvendorid CSR.

    [1] https://github.com/openocd-org/openocd/blob/1ebff3ab33c77e3f8fb4e1ddda262b606b572af1/src/helper/jep106.inc#L1935

    Signed-off-by: Joel Stanley <joel@jms.id.au>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Michael Ellerman <mpe@oss.tenstorrent.com>
    Message-ID: <20260114020516.982305-1-joel@jms.id.au>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 38286b6b40..72c6f4f0f1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3207,6 +3207,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .cfg.ext_svnapot = true,
         .cfg.ext_svpbmt = true,

+        .cfg.mvendorid = TENSTORRENT_VENDOR_ID,
+
         .cfg.max_satp_mode = VM_1_10_SV57,
     ),

diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
index f1ffc66542..751a13aace 100644
--- a/target/riscv/cpu_vendorid.h
+++ b/target/riscv/cpu_vendorid.h
@@ -8,4 +8,6 @@
 #define VEYRON_V1_MIMPID        0x111
 #define VEYRON_V1_MVENDORID     0x61f

+#define TENSTORRENT_VENDOR_ID   0x7a1
+
 #endif /*  TARGET_RISCV_CPU_VENDORID_H */