Commit e0c0ea6eca for qemu.org

commit e0c0ea6eca4f210a52b9742817586cc97b1ee434
Author: Alexandra Diupina <adiupina@astralinux.ru>
Date:   Mon Oct 14 17:05:50 2024 +0100

    hw/intc/arm_gicv3: Add cast to match the documentation

    The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
    When cast to uint64_t (for further bitwise OR), the 32 most
    significant bits will be filled with 1s. However, the documentation
    states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.

    Add an explicit cast to match the documentation.

    Found by Linux Verification Center (linuxtesting.org) with SVACE.

    Cc: qemu-stable@nongnu.org
    Fixes: d2c0c6aab6 ("hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()")
    Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
    Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index bdb13b00e9..ebad7aaea1 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -781,7 +781,7 @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp)
     if (nmi) {
         cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI;
     } else {
-        cs->ich_apr[grp][regno] |= (1 << regbit);
+        cs->ich_apr[grp][regno] |= (1U << regbit);
     }
 }