Commit e868257fe6 for qemu.org

commit e868257fe6887c26d635d3156aff8d41e1f4a879
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Wed Feb 18 18:40:14 2026 +0000

    target/arm: Add aa64_sme_or_sve, aa64_sme_or_sve2 features

    With FEAT_SME, even a CPU which does not implement FEAT_SVE is
    allowed to execute the subset of SVE instructions which are permitted
    in streaming SVE mode.  We correctly handle this when the emulated
    CPU has both FEAT_SVE and FEAT_SME, because sve_access_check()
    includes the logic for this, matching the pseudocode
    CheckSVEEnabled().  However if the emulated CPU only implement
    FEAT_SME, it will fail the initial dc_isar_feature(aa64_sve, s)
    feature check, because this doesn't match the check in the
    per-instruction decode pseudocode, which is typically:

     !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)

    Add a new aa64_sme_or_sve feature function that we can use
    to update the relevant uses of aa64_sve, and similarly
    aa64_sme_or_sve2 for where we need to check FEAT_SVE2 || FEAT_SME.

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Message-id: 20260202133353.2231685-9-peter.maydell@linaro.org

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 49c50e850a..6935ef2f78 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1522,6 +1522,16 @@ static inline bool isar_feature_aa64_sme2p1(const ARMISARegisters *id)
 /*
  * Combinations of feature tests, for ease of use with TRANS_FEAT.
  */
+static inline bool isar_feature_aa64_sme_or_sve(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_sme(id) || isar_feature_aa64_sve(id);
+}
+
+static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id);
+}
+
 static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)
 {
     return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);