Commit ee437322f4 for qemu.org
commit ee437322f4a06c07ab68e5e68d8e8fc699399a9d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Thu Aug 6 10:27:08 2026 -0700
target/arm: Set fgt in cpregs for FGWTE3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260806172709.333300-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c
index e31827342d..9c9ae9cd71 100644
--- a/target/arm/cpregs-gcs.c
+++ b/target/arm/cpregs-gcs.c
@@ -97,7 +97,7 @@ static const ARMCPRegInfo gcs_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[2]) },
{ .name = "GCSCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 5, .opc2 = 0,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_GCSCR_EL3,
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[3]) },
{ .name = "GCSPR_EL0", .state = ARM_CP_STATE_AA64,
@@ -119,7 +119,8 @@ static const ARMCPRegInfo gcs_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[2]) },
{ .name = "GCSPR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 5, .opc2 = 1,
- .access = PL3_RW, .writefn = gcspr_write,
+ .access = PL3_RW, .fgt = FGT_GCSPR_EL3,
+ .writefn = gcspr_write,
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[2]) },
{ .name = "GCSPUSHM", .state = ARM_CP_STATE_AA64,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1b24aca293..c3f607e6d6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1056,7 +1056,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.resetvalue = 0 },
{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
+ .access = PL3_RW, .fgt = FGT_MAIR_EL3,
+ .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
.resetvalue = 0 },
/*
* For non-long-descriptor page tables these are PRRR and NMRR;
@@ -3728,7 +3729,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.type = ARM_CP_IO,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
.resetvalue = 0,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_MDCR_EL3,
.writefn = mdcr_el3_write,
.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
@@ -4498,11 +4499,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
{ .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
- .access = PL3_RW, .resetvalue = 0,
+ .access = PL3_RW, .fgt = FGT_TTBR0_EL3,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
{ .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_TCR_EL3,
/* no .writefn needed as this can't cause an ASID change */
.resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
@@ -4524,7 +4525,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
{ .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
- .access = PL3_RW, .writefn = vbar_write,
+ .access = PL3_RW, .fgt = FGT_VBAR_EL3, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
.resetvalue = 0 },
{ .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
@@ -4533,20 +4534,20 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
{ .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
- .access = PL3_RW, .resetvalue = 0,
+ .access = PL3_RW, .fgt = FGT_TPIDR_EL3,
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
{ .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
- .access = PL3_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .access = PL3_RW, .fgt = FGT_AMAIR_EL3,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
- .access = PL3_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .access = PL3_RW, .fgt = FGT_AFSR0_EL3,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
- .access = PL3_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .access = PL3_RW, .fgt = FGT_AFSR1_EL3,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
};
#ifndef CONFIG_USER_ONLY
@@ -5114,15 +5115,17 @@ static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri,
static const ARMCPRegInfo rme_reginfo[] = {
{ .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
- .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset,
+ .access = PL3_RW, .fgt = FGT_GPCCR_EL3,
+ .writefn = gpccr_write, .resetfn = gpccr_reset,
.fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) },
{ .name = "GPCBW_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 5,
- .access = PL3_RW, .writefn = gpcbw_write,
+ .access = PL3_RW, .fgt = FGT_GPCBW_EL3, .writefn = gpcbw_write,
.fieldoffset = offsetof(CPUARMState, cp15.gpcbw_el3) },
{ .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },
+ .access = PL3_RW, .fgt = FGT_GPTBR_EL3,
+ .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },
{ .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) },
@@ -5232,7 +5235,7 @@ static const ARMCPRegInfo mec_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.mecid_a1_el2) },
{ .name = "MECID_RL_A_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .opc2 = 1, .crn = 10, .crm = 10,
- .access = PL3_RW, .accessfn = mecid_access,
+ .access = PL3_RW, .accessfn = mecid_access, .fgt = FGT_MECID_RL_A_EL3,
.writefn = mecid_write,
.fieldoffset = offsetof(CPUARMState, cp15.mecid_rl_a_el3) },
{ .name = "VMECID_P_EL2", .state = ARM_CP_STATE_AA64,
@@ -6182,7 +6185,7 @@ static const ARMCPRegInfo sctlr2_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.sctlr2_el[2]) },
{ .name = "SCTLR2_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .opc2 = 3, .crn = 1, .crm = 0,
- .access = PL3_RW, .writefn = sctlr2_el3_write,
+ .access = PL3_RW, .fgt = FGT_SCTLR2_EL3, .writefn = sctlr2_el3_write,
.fieldoffset = offsetof(CPUARMState, cp15.sctlr2_el[3]) },
};
@@ -6308,7 +6311,7 @@ static const ARMCPRegInfo s1pie_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[2]) },
{ .name = "PIR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .opc2 = 3, .crn = 10, .crm = 2,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_PIR_EL3,
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[3]) },
{ .name = "PIRE0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 10, .crm = 2,
@@ -6366,7 +6369,7 @@ static const ARMCPRegInfo aie_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[2]) },
{ .name = "MAIR2_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 1, .opc2 = 1,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_MAIR2_EL3,
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[3]) },
{ .name = "AMAIR2_EL1", .state = ARM_CP_STATE_AA64,
@@ -6382,7 +6385,7 @@ static const ARMCPRegInfo aie_reginfo[] = {
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "AMAIR2_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 1,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_AMAIR2_EL3,
.type = ARM_CP_CONST, .resetvalue = 0 },
};
@@ -7110,7 +7113,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
- .access = PL3_RW,
+ .access = PL3_RW, .fgt = FGT_SCTLR_EL3,
.raw_writefn = raw_write, .writefn = sctlr_write,
.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
.resetvalue = cpu->reset_sctlr },
@@ -7485,8 +7488,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.resetvalue = 0 },
{ .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
- .access = PL3_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .access = PL3_RW, .fgt = FGT_ACTLR_EL3,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
};
define_arm_cp_regs(cpu, auxcr_reginfo);
if (cpu_isar_feature(aa32_ac2, cpu)) {