Commit ef1e8668b9 for qemu.org
commit ef1e8668b9f3ab6d6e7826806db1de5326f9df7d
Merge: 93b9a24365 90789a83fb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: Wed Sep 2 11:11:14 2026 +0100
Merge tag 'pull-target-arm-20260901' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* target/arm: fix TTA instruction S bit for IDAU-exempt addresses
* target/arm: Correct reset value of SCTLR for arm926, arm1026
* target/arm: Don't provide TLBTR for pre-v6 CPUs
* target/arm: Don't enforce alignment faults on Device memory for SCTLR.U == 0
* target/arm: Correctly UNDEF Thumb T1 hints, CBZ, IT on older CPUs
* target/arm: add cortex-m85 model
* target/arm: Separate cpu types max-v8 and max-v9
* target/arm: Implement FEAT_FGWTE3, FEAT_SVE2p2, FEAT_SME2p2,
FEAT_SVE_BFSCALE, FEAT_SSVE_BitPerm, FEAT_SVE_AES2
* hw/char/pl011: support backend hotswap
* hw/arm: Add Arm mps3-an555 board
* hw/arm: Remove the 'musicpal' machine
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmqW0CAZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3upND/4oA0l9D6xr/F19oaSC0Zy7
# qodQl1zeDTfcvNmh/e72KKXJKG1+FBYDBSjqlekrj0/TV+pEzQZANItVZE21m9SR
# +GZ5WBzBmR5V0UuZQSZZiVqBGbXwt8qZz0wMez5W7JncofIiU0GxuTYAdN0NHxub
# sYSYYHOrQQCTW7BJlfImN9nD4qXzshrEuVWlszNIjc7Qh5vgja6juDkOF4En3g7w
# zWUtvzbGMWcPmYZmtbCCY9u8YnUOPdohB1blYOjLvMHn4+GqBlkjN93ytWw0J5CM
# eS3qs2pZWs/zEUGXEhymUqI3qXQflo0tCES9OsY40kExBu5YjYXBT93tBEdkwX8+
# CFK8eC26DRqcbFHv6CPnYYxy0dzUvAR4s4cpYXFrKQlJI6I8cwKNWYeLaISHak7i
# Emg2Hzo7+M3UV5oKiYJY+HG3EA3DZYfWq4lIAmTVOhSs6/na9Hr41FBWFy93VLnE
# 7/Db1BnOrdBrMvEIUvEnM2o6XaH6cICID7W/OHvhTMEW/1X7gq8pJsFJ/NcP+d2f
# 4Fuj1y0RCuFY3SVB2TI/PpVflfJmBD7i+gezoygE2h9MVF2fIxTd0AXFxwEfQiQW
# jVqiyCAel32c4Bey1GFrIUzCsRPfg6eCvOyLXqULgyA6ksTreV5P9D31ydaUvIMY
# ohAhu+1LpVjIoCTeq72Abw==
# =/OvS
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue Sep 1 14:16:16 2026 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260901' of https://gitlab.com/pm215/qemu: (58 commits)
target/arm: Enable FEAT_SVE_AES2 for -cpu max
target/arm: Implement PMULL, PMLAL
target/arm: Implement AESDIMC
target/arm: Implement AESEMC
target/arm: Implement AESD (indexed)
target/arm: Implement AESE (indexed)
target/arm: Implement and enable FEAT_SSVE_BitPerm for -cpu max
target/arm: Rename isar_feature_aa64_sve_sm4
target/arm: Rename isar_feature_aa64_sve_sha3
target/arm: Rename isar_feature_aa64_sve_bitperm
target/arm: Rename isar_feature_aa64_sve_pmull128
target/arm: Enable FEAT_SVE_BFSCALE for -cpu max
target/arm: Implement SME BFMUL
target/arm: Implement SME BFSCALE
target/arm: Implement SVE BFSCALE
target/arm: Split decode of BFloat SVE FADD, FSUB, FMUL, FMIN*, FMAX*
target/arm: Remove DO_ZPZZ_AH_FP_B16 from translate-sme.c
target/arm: Remove DO_ZPZZ_AH_FP from translate-sme.c
target/arm: Remove DO_ZPZZ_FP_B16 from translate-sme.c
target/arm: Remove DO_ZPZZ_FP from translate-sme.c
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>