Commit 74f7bf4c59 for qemu.org
commit 74f7bf4c59e6b6d50dbc6e124d93440be8be4386
Merge: 812798d748 cbad21fae0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Mon Nov 2 20:19:27 2026 -0800
Merge tag 'pull-target-arm-20261102-1' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* raspi4b: Implement PCI and GENET ethernet device
* target/arm: Initialize SMCR_EL1.EZT0 for linux-user
* hw/dma/xlnx_dpdma: Don't allow DMA off end of host buffers
* target/arm: For linux-user, prioritize PC misalignment fault over insn abort
* net/tap: Avoid "close(-1)" in net_init_tap() error path
* hvf: arm: save/restore SME state only when SME on
* hvf: arm: advertise ID_AA64PFR0_EL1.GIC correctly
* target/arm: Refactoring preparatory to ID register configurability
* target/arm/cpu64: Define cpreg migration tolerance for PMMIR_EL1
* gicv5: minor cleanups and bugfixes
* target/arm: hold bql when SEV sets the event_register
* target/arm: fix bcm2835 migration issue
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# gpg: Signature made Mon 02 Nov 2026 09:08:52 AM PST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [unknown]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20261102-1' of https://gitlab.com/pm215/qemu: (46 commits)
target/arm: fix bcm2835 migration issue
target/arm: don't pass env to the sev helper
target/arm: hold bql when SEV sets the event_register
hw/intc/arm_gicv5: Relax QEMU_GICV5_MIN_LPI_ID_BITS to 0
hw/intc/arm_gicv5: Pass cpuidx rather than iaffid in gicv5_get_hppi()
hw/intc/arm_gicv5: Pass CPU index to CPU interface
target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status
hw/intc/arm_gicv5: Regularize spacing in config_readl() switch
hw/intc/arm_gicv5: Ignore low bits in L1_ISTE.L2_ADDR
hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR
target/arm/cpu64: Define cpreg migration tolerance for PMMIR_EL1
target/arm/cpu64: fix typos in kvm_arm_set_cpreg_mig_tolerances()
target/arm/kvm: Improve error handling on scratch vcpu probe
target/arm: Directly store cpu probe failure error
hw/arm/virt: Make sure virt_get_caches() keeps on reading CLIDR_EL1 as 0
target/arm/kvm: Introduce kvm_arm_vcpu_prepare_init_features helper
target/kvm: Pass an Error handle to kvm_arch_init_vcpu
target/arm/kvm: Pass an error handle to kvm_arm_init_cpreg_list
target/arm: Enforce MPIDR into isar.idregs[] storage
target/arm: Move MIDR into isar.idregs[] storage
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>