Commit c513597761 for qemu.org
commit c513597761d6fc06690b5b7cf10dfb7ab05815d0
Merge: a925240509 4a4ba15b2b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: Wed Sep 2 17:59:30 2026 +0100
Merge tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu into staging
semihosting, fix exc/int, icinva, TLB, htid
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# gpg: Signature made Wed Sep 2 05:37:46 2026 BST
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [full]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [full]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [full]
# gpg: aka "bcain" [full]
# gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu: (28 commits)
hw/hexagon: decode an empty TLB size field as 4KB
hw/hexagon: assign a distinct htid to each DSP machine CPU
tests/tcg/hexagon: add icinva test
target/hexagon: invalidate translated code for user icinva
tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs}
target/hexagon: fix iassign{r, w} to cover all threads
target/hexagon: implement direct-to-guest interrupt delivery
target/hexagon: raise imprecise exception on multi-TLB match
target/hexagon: read UTIMERLO/UTIMERHI from the global timer
target/hexagon: gate GPCYCLE guest register reads on SSR:CE
target/hexagon: take BQL when reading the system pcycle count
target/hexagon: guard writes to unimplemented guest registers
hw/intc: clear pending bit on l2vic de-assertion
tests/tcg/hexagon: check priv instructions raise SIGILL
target/hexagon: align exceptions for user/sysemu
tests/functional: Add hexagon semihosting systests
python/machine: support routing semihosting output to the test console
target/hexagon: Add an errno mapping
target/hexagon: add COREDUMP semihosting operation
target/hexagon: add main arch-specific semihosting operations
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# hw/hexagon/hexagon_tlb.c
diff --cc hw/hexagon/hexagon_tlb.c
index ed8c0a7612,d89e4161f1..c76805abac
--- a/hw/hexagon/hexagon_tlb.c
+++ b/hw/hexagon/hexagon_tlb.c
@@@ -57,8 -56,19 +57,6 @@@ typedef enum
#define NUM_PGSIZE_TYPES (PGSIZE_1G + 1)
- #define INVALID_MASK 0xffffffffLL
-static const char *pgsize_str[NUM_PGSIZE_TYPES] = {
- "4K",
- "16K",
- "64K",
- "256K",
- "1M",
- "4M",
- "16M",
- "64M",
- "256M",
- "1G",
-};
--
static const uint64_t encmask_2_mask[] = {
0x0fffLL, /* 4k, 0000 */
0x3fffLL, /* 16k, 0001 */