Commit 7b153cf30c for qemu.org

commit 7b153cf30cec0a1f8dfe8bc12fb4414b556aac22
Author: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Date:   Mon Aug 24 08:58:11 2026 -0700

    target/hexagon: fix store-conditional on big-endian hosts

    gen_load_locked4u() and gen_load_locked8u() read guest memory with an
    explicit MO_LE, but gen_store_conditional4() and
    gen_store_conditional8() are missing that, so we wrongly access guest
    memory in host byte order.

    Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
    Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 2a98b13b71..9330732c99 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -576,7 +576,7 @@ static inline void gen_store_conditional4(DisasContext *ctx,
     zero = tcg_constant_tl(0);
     tmp = tcg_temp_new();
     tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
-                              ctx->mem_idx, MO_32 | MO_ALIGN);
+                              ctx->mem_idx, MO_LE | MO_32 | MO_ALIGN);
     tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
                        one, zero);
     tcg_gen_br(done);
@@ -601,7 +601,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,
     zero = tcg_constant_i64(0);
     tmp = tcg_temp_new_i64();
     tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
-                               ctx->mem_idx, MO_64 | MO_ALIGN);
+                               ctx->mem_idx, MO_LE | MO_64 | MO_ALIGN);
     tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
                         one, zero);
     tcg_gen_extrl_i64_i32(pred, tmp);