Commit 1b8b67503725 for kernel

commit 1b8b67503725fa6deb3a4f00ea61f982bd00c152
Merge: fb7bd3a2aad7 a5ae1bf65cee
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Thu Oct 29 12:33:25 2026 -1000

    Merge tag 'riscv-for-linus-7.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

    Pull RISC-V updates from Paul Walmsley:

     - Add support for crash hotplug

     - Improve user copy performance on cores with fast misaligned accesses

     - Optimize code paths involving pgtable_l{4,5}_enabled() by patching in
       the return values during early boot (since these don't change during
       runtime), or by specifying the return values directly in Kconfig
       files (for purpose-built kernels)

     - Change the PCIe bus reassignment behavior to depend on the
       PCI_REASSIGN_ALL_BUS PCI flag (as ARM64 does)

     - Avoid an unnecessary sstatus CSR read during context switch

     - Make the sbi_ecall() macro variadic, improving code clarity

     - Refactor __switch_to_vector() to prepare for upcoming vector context
       switch optimizations

     - Add a kselftest for vectorized user copy

     - Add bounds checking on the shadow stack restore token address to
       avoid it being used as an attack vector

     - Fix the shadow stack and indirect branch landing pad control
       functions to only update the CPU's envcfg CSR when operating on the
       current task

     - For MIPS RISC-V systems, add support for early boot-applied errata;
       and for P8700 RISC-V systems, avoid WFI usage in the kernel (since it
       is buggy)

     - Add the "B" RISC-V ISA extension to hwcap and hwprobe reporting

     - Add support for specifying and reporting the "Zic64b" RISC-V ISA
       extension, and add it to the SpacemiT K1, K3, and Sophgo SG2044 DT
       files

     - Require the block size of cache management operations to be specified
       in DT schema validation for the RISC-V ISA extensions Zicbom, Zicbop,
       and Zicboz

     - Some miscellaneous fixes: fix an incorrect bitfield width in the
       RVG_SYSTEM_CSR_MASK bitmask macro; make RISCV_ALTERNATIVE mandatory,
       now that XIP kernel support has been removed; and remove some
       unnecessary includes in kernel/smp.c

    * tag 'riscv-for-linus-7.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits)
      riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled
      riscv: introduce RISCV_ISA_SV48 and RISCV_ISA_SV57
      riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled
      riscv: convert pgtable_l4|l5_enabled to inline function
      riscv: remove RISCV_ALTERNATIVE Kconfig option
      riscv: Add a getter for user PMLEN support
      riscv: dts: sophgo: sg2044: Add Zic64b ISA extension
      riscv: dts: spacemit: k1: Add Zic64b ISA extension
      riscv: dts: spacemit: k3: Add Zic64b ISA extension
      riscv: Add Zic64b to cpufeature and hwprobe
      dt-bindings: riscv: Add Zic64b extension description
      dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz
      riscv: Add B to hwcap and hwprobe
      riscv: remove unused profile.h includes
      riscv: cfi: Only write envcfg CSR when task is current
      riscv: cfi: Bounds check restore token before swap
      riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pause
      selftest: riscv: test vectorized user copy
      riscv: vector: refactor context switch for kernel-mode vector
      riscv: do not read csr in vector context switch
      ...

diff --cc arch/riscv/include/asm/pgtable-64.h
index ae23182b572c,caf8458b344c..eb7708e35cf9
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@@ -264,9 -298,18 +298,9 @@@ static inline unsigned long _pmd_pfn(pm
  	return __page_val_to_pfn(pmd_val(pmd));
  }

 -#define pmd_ERROR(e) \
 -	pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
 -
 -#define pud_ERROR(e)   \
 -	pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
 -
 -#define p4d_ERROR(e)   \
 -	pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e))
 -
  static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
  {
- 	if (pgtable_l4_enabled)
+ 	if (pgtable_l4_enabled())
  		WRITE_ONCE(*p4dp, p4d);
  	else
  		set_pud((pud_t *)p4dp, (pud_t){ p4d_val(p4d) });