Commit 2d60589595 for qemu.org

commit 2d60589595b66bcb24c2fb2dbb79d018cb4db053
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date:   Sat Sep 26 19:43:44 2026 -0700

    target/hexagon: clear LL/SC reservations at context boundaries

    Set llsc_addr to ~0 during reset and soft reset, and whenever linux-user
    returns to guest code for a trap or a signal.

    Reset previously left llsc_addr zero-initialized, so a store-conditional
    issued without a matching load-locked could match a guest address of
    zero.

    Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index e4ef97a118..e6bb3b62a9 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -39,6 +39,10 @@ void cpu_loop(CPUHexagonState *env)
         cpu_exec_end(cs);
         qemu_process_cpu_events(cs);

+        if (trapnr != EXCP_ATOMIC && trapnr != EXCP_YIELD) {
+            env->llsc_addr = ~0;
+        }
+
         switch (trapnr) {
         case EXCP_INTERRUPT:
             /* just indicate that signals should be handled asap */
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index a74eaa45fc..5ae2026eb2 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -411,6 +411,7 @@ void hexagon_cpu_soft_reset(CPUHexagonState *env)
     HexagonCPU *cpu;

     BQL_LOCK_GUARD();
+    env->llsc_addr = ~0;
     env->t_sreg[HEX_SREG_SSR] = 0;
     hexagon_ssr_set_cause(env, HEX_CAUSE_RESET);

@@ -446,6 +447,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)

     set_default_nan_mode(1, &env->hvx_fp_status);
     set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status);
+
+    env->llsc_addr = ~0;
 #ifndef CONFIG_USER_ONLY
     memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS);
     memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS);