Commit 329107ed37 for qemu.org

commit 329107ed376189b9c786c6594677751bf80efebd
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date:   Thu Oct 15 06:36:30 2026 +0000

    hw/arm/aspeed_ast1040: Add AST1080 SoC support

    Add initial support for the Aspeed AST1080 SoC. The AST1080 reuses most
    of the AST1040 peripheral device models, as the two SoCs share nearly
    the same controllers including WDT, SCU, GPIO, SGPIO, ADC, I2C, FMC,
    and SPI.

    The common initialization and realization functions,
    aspeed_soc_ast10x0_g2_init() and aspeed_soc_ast10x0_g2_realize(),
    introduced in the previous patches are reused, so AST1080 can
    instantiate the existing AST1040 device models without defining
    duplicate device types.

    Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
    Reviewed-by: Cédric Le Goater <clg@redhat.com>
    Link: https://lore.kernel.org/qemu-devel/20261015063625.186708-5-jamin_lin@aspeedtech.com
    Signed-off-by: Cédric Le Goater <clg@redhat.com>

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index 28abbe7010..c641f84fbe 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -162,6 +162,11 @@ static void aspeed_soc_ast1040_init(Object *obj)
     object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
 }

+static void aspeed_soc_ast1080_init(Object *obj)
+{
+    aspeed_soc_ast10x0_g2_init(obj);
+}
+
 static bool aspeed_soc_ast10x0_g2_realize(Aspeed10x0SoCState *a, Error **errp)
 {
     AspeedSoCState *s = ASPEED_SOC(a);
@@ -342,6 +347,15 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
                        aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_PECI));
 }

+static void aspeed_soc_ast1080_realize(DeviceState *dev_soc, Error **errp)
+{
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
+
+    if (!aspeed_soc_ast10x0_g2_realize(a, errp)) {
+        return;
+    }
+}
+
 static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
 {
     static const char * const valid_cpu_types[] = {
@@ -370,12 +384,45 @@ static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
     sc->num_cpus        = 1;
 }

+static void aspeed_soc_ast1080_class_init(ObjectClass *klass, const void *data)
+{
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+        NULL
+    };
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+    /* Reason: The Aspeed SoC can only be instantiated from a board */
+    dc->user_creatable = false;
+    dc->realize = aspeed_soc_ast1080_realize;
+
+    sc->valid_cpu_types = valid_cpu_types;
+    sc->silicon_rev     = AST1080_A0_SILICON_REV;
+    sc->sram_size[0]    = 128 * KiB;
+    sc->sram_size[1]    = 16 * MiB; /* Hyper RAM */
+    sc->uarts_num       = 13;
+    sc->sgpio_num       = 1;
+    sc->wdts_num        = 8;
+    sc->spis_num        = 2;
+    sc->uarts_base      = ASPEED_DEV_UART0;
+    sc->irqmap          = aspeed_soc_ast1040_irqmap;
+    sc->memmap          = aspeed_soc_ast1040_memmap;
+    sc->num_cpus        = 1;
+}
+
 static const TypeInfo aspeed_soc_ast1040_types[] = {
     {
         .name           = "ast1040-a0",
         .parent         = TYPE_ASPEED10X0_SOC,
         .instance_init  = aspeed_soc_ast1040_init,
         .class_init     = aspeed_soc_ast1040_class_init,
+    },
+    {
+        .name           = "ast1080-a0",
+        .parent         = TYPE_ASPEED10X0_SOC,
+        .instance_init  = aspeed_soc_ast1080_init,
+        .class_init     = aspeed_soc_ast1080_class_init,
     }
 };