Commit 3876503faf for qemu.org
commit 3876503faff51ce3a132dbbd0ab42c10f2269319
Merge: a97f90fcf8 cbbd4d74eb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Thu Sep 24 13:30:19 2026 -0700
Merge tag 'target-misc-20260924' of https://github.com/philmd/qemu into staging
Misc target patches queue
- DOC: Improve SysemuCPUOps::has_work docstring
- MIPS: Let TCG middle-end optimize MXU opcodes (not front-end)
- S390x: Access S390CpuState atomically
- ARM: Access halt/PSCI states atomically
- X86: Access interrupt_request atomically
- PPC: Fix double-free in ppc_cpu_unrealize()
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmq1QGEACgkQ4+MsLN6t
# wN46Kw//QWsLWdmuJ8hRh34xMYBnJFtRG9DkrTpvoQAGo+0xHm3E3JGxWzxyiL98
# UfXQgQgVwgsT/cfWIZ/BKI6gBMfkzFdXYrlywEb3KS4JXGUVcMOgMd9dULjgatFw
# Y1oKDSlVH/kt28vuYTTlQ7p2uAIMwQVF/4wmSQInAqGROTK0lu2l/zmzG1hX39Pk
# E+8BZ3HhIRGIIyC9cKSr7z4qg562XM1KLrdCNC84YAESvnFbKzz7qBjcPltz+J4s
# z889rjEKhfsMowU14OyxUj7khr7/iQoStaPJqWm5C9kVTe1OSTjLqD0+iQ5Syw8z
# Pu3SLq0s25UlHZInLuVKZ5FvlZTkRha1D2dfqSFAfebM+DJXlfKH6QTpJRF3HiD+
# XsJeg2HZ+jXc0yhf8p8ZstEI68ChUItltCrGv2Og8bpHFI9iDW79kwfYNyYsR+g0
# sE4uaP+xM5Z8C9SLJDdXJ2vn1ZiLn9tFh00iIn1rQl9ienT73deZWe4znBlAORJZ
# GZOrd4Duf1I8ybPGa2KJ6MA4v4v8UOxr6lmX8lXnxsXrN552oRS52Qj3XL4cSbSM
# nAPCEK0ljTeZBCCrPtjcr5D/j/HXQ0Uo+/bXfYP+JSmzhwMgOdITUo8VYKmpq9CL
# DaHblfrkthH14oLTi1XzWK1RbfeqwYuXsnUw3njSkJgAmoFFjwY=
# =RbtM
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Sep 2026 08:23:13 AM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'target-misc-20260924' of https://github.com/philmd/qemu:
target/ppc: Stop vCPU thread before calling parent_unrealize
target/i386: Use an acquire load for interrupt_request()
target/arm: Access halt state atomically
target/arm: Access PSCI state atomically
target/arm: Un-inline arm_set_cpu_power_state()
target/s390x: Access S390CpuState atomically
target/s390x: Use S390CpuState for CPU state APIs
target/s390x: Make s390_cpu_set_state() return void
target/s390x: Extend comment about PV cpu load state
target/s390x: Use s390_cpu_get_state() consistently
system: Document has_work() synchronization requirements
target/riscv: Stub out kvm functions
target/mips: Use gen_mxu_logic for gen_mxu_S32CPS
target/mips: Use gen_mxu_logic for gen_mxu_S32SLT
target/mips: Use gen_mxu_logic for gen_mxu_S32MAX_S32MIN
target/mips: Split out gen_mxu_logic
target/mips: Drop zero optimization in gen_mxu_s32mul
target/mips: Fix zero in gen_mxu_d8sum
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>