Commit 414ad1be16 for qemu.org

commit 414ad1be16c8998f41a2e7776245d4003c904123
Author: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Date:   Mon Sep 28 17:11:03 2026 -0300

    target/riscv: add riscv-server-ref CPU

    The harts requirements of RISC-V server platform [1] require RVA23 ISA
    profile support and others.

    We're going for a profile-based implementation, instead of a regular CPU
    that can inherit RVA23, to allow future CPUs to use it internally as a
    starting base for their own extension sets.  There's also a new
    'rvserver-ref-1.0' flag that can be used to set the extensions in the
    command line for other CPUs, which can be used for testing/debugging
    purposes.

    Note that for all intents and purposes "riscv-server-ref" is a regular
    CPU and no, we're not trying to set a precedent of calling the riscv
    server platform spec a profile.

    [1] defines in rule SEE_020 that we must support at least 11 debug
    triggers (4 for insn address, 4 for insn load/store, 1 for icount,
    one for int, one for excp).  We're going for the minimum.  If more
    triggers are needed users can set any trigger amount (N <= 1024)
    with:

    -cpu riscv-server-ref,num-triggers=N

    [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc

    Suggested-by: Icenowy Zheng <uwu@icenowy.me>
    Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
    Reviewed-by: Chao Liu <chao.liu@processmission.com>
    Reviewed-by: Sunil V L <sunilvl@oss.qualcomm.com>
    Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
    Message-ID: <20260928201107.2049458-3-daniel.barboza@oss.qualcomm.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1a28f1369c..61234842e3 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -42,6 +42,7 @@
 #define TYPE_RISCV_CPU_RVA22S64         RISCV_CPU_TYPE_NAME("rva22s64")
 #define TYPE_RISCV_CPU_RVA23U64         RISCV_CPU_TYPE_NAME("rva23u64")
 #define TYPE_RISCV_CPU_RVA23S64         RISCV_CPU_TYPE_NAME("rva23s64")
+#define TYPE_RISCV_CPU_RVSERVER_REF     RISCV_CPU_TYPE_NAME("riscv-server-ref")
 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
 #define TYPE_RISCV_CPU_SIFIVE_E         RISCV_CPU_TYPE_NAME("sifive-e")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 658a8162dd..306be10d10 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2437,11 +2437,37 @@ static RISCVCPUProfile RVA23S64 = {
     }
 };

+/*
+ * This riscv-server-ref entry isn't a profile per se but its
+ * CPU definition can be modelled as a profile that extends
+ * RVA23, with additional things on top of it, and allowing
+ * future CPUs to derive from it via
+ * ".profile = &RVServerRef1_0;".
+ */
+static RISCVCPUProfile RVServerRef1_0 = {
+    .s_parent = &RVA23S64,
+    .name = "riscv-server-ref-1.0",
+    .satp_mode = VM_1_10_SV48,
+    .priv_spec = PRIV_VERSION_1_13_0,
+    .ext_offsets = {
+        CPU_CFG_OFFSET(ext_zkr),
+        CPU_CFG_OFFSET(ext_sdext),
+        CPU_CFG_OFFSET(ext_sdtrig),
+        CPU_CFG_OFFSET(ext_ssaia),
+        CPU_CFG_OFFSET(ext_ssccfg),
+        /* ssstrict is always enabled for PRIV_VER_1_12+ */
+
+        RISCV_PROFILE_EXT_LIST_END
+    }
+};
+
+
 RISCVCPUProfile *riscv_profiles[] = {
     &RVA22U64,
     &RVA22S64,
     &RVA23U64,
     &RVA23S64,
+    &RVServerRef1_0,
     NULL,
 };

@@ -3829,6 +3855,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
 #endif
     ),

+    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU,
+        .profile = &RVServerRef1_0,
+        .misa_mxl_max = MXL_RV64,
+        .cfg.max_satp_mode = VM_1_10_SV57,
+        .cfg.pmu_mask = MAKE_64BIT_MASK(3, 6),
+        .num_triggers = 11,
+    ),
+
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
     DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
         .cfg.max_satp_mode = VM_1_10_SV57,