Commit 7720966392 for qemu.org
commit 77209663924e969411ff9fff280a4090382ebceb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Mon Sep 14 11:59:16 2026 -1000
target/i386/tcg: Always initialize CCPrepare.reg
Forthcoming tcg improvements will diagnose the passed
null pointer with --enable-ubsan:
../src/target/i386/tcg/translate.c:1177:5: runtime error: null pointer passed as argument 3, which is declared to never be null
#0 ... in gen_setcc ../src/target/i386/tcg/translate.c:1177
#1 ... in gen_compute_eflags_c ../src/target/i386/tcg/translate.c:1182
#2 ... in prepare_update_cc_incdec ../src/target/i386/tcg/emit.c.inc:407
#3 ... in gen_INC ../src/target/i386/tcg/emit.c.inc:2213
#4 ... in disas_insn ../src/target/i386/tcg/decode-new.c.inc:3151
#5 ... in i386_tr_translate_insn ../src/target/i386/tcg/translate.c:3514
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d8de290acb..192cf43215 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -891,7 +891,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
case CC_OP_LOGICB ... CC_OP_LOGICQ:
case CC_OP_POPCNT:
- return (CCPrepare) { .cond = TCG_COND_NEVER };
+ return (CCPrepare) { .cond = TCG_COND_NEVER, .reg = cpu_cc_dst };
case CC_OP_INCB ... CC_OP_INCQ:
case CC_OP_DECB ... CC_OP_DECQ:
@@ -965,7 +965,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.imm = CC_S };
case CC_OP_POPCNT:
- return (CCPrepare) { .cond = TCG_COND_NEVER };
+ return (CCPrepare) { .cond = TCG_COND_NEVER, .reg = cpu_cc_dst };
default:
return gen_prepare_sign_nz(cpu_cc_dst, cc_op_size(s->cc_op));
}
@@ -982,7 +982,7 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
case CC_OP_SBB_SELF:
case CC_OP_LOGICB ... CC_OP_LOGICQ:
case CC_OP_POPCNT:
- return (CCPrepare) { .cond = TCG_COND_NEVER };
+ return (CCPrepare) { .cond = TCG_COND_NEVER, .reg = cpu_cc_dst };
case CC_OP_MULB ... CC_OP_MULQ:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src };
default: