Commit 7d30199707 for qemu.org

commit 7d30199707819cbc9ad4f58d253f2ea662cf523b
Author: Frank Chang <frank.chang@sifive.com>
Date:   Sun Sep 27 16:25:31 2026 +0800

    target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules

    Add SiFive custom int8 matmul extension implied rules to enable the
    implied extensions of SiFive custom int8 matmul extension recursively.

    Signed-off-by: Frank Chang <frank.chang@sifive.com>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Signed-off-by: Max Chou <max.chou@sifive.com>
    Reviewed-by: Chao Liu <chao.liu@processmission.com>
    Message-ID: <20260927082534.3228237-4-max.chou@sifive.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f99698b83e..9e3d096802 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2920,6 +2920,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
     },
 };

+static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
+static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
     &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
     &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
@@ -2971,6 +2989,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &SMCTR_IMPLIED,
     &SSCTR_IMPLIED,
     &SSSTATEEN_IMPLIED,
+    &XSFVQMACCDOD_IMPLIED,
+    &XSFVQMACCQOQ_IMPLIED,
     NULL
 };