Commit 7f12f1308d for openssl.org

commit 7f12f1308d6b49c5d4fee008ed333beeb025c69d
Author: George Pantelakis <gpantela@redhat.com>
Date:   Tue Sep 29 15:17:44 2026 +0200

    Check ARM CAPS for NEON if OPENSSL_armcap is provided

    Reviewed-by: Tom Cosgrove <tom.cosgrove@arm.com>
    Reviewed-by: Dmitry Belyavskiy <beldmit@gmail.com>
    MergeDate: Thu Oct  1 16:08:23 2026
    (Merged from https://github.com/openssl/openssl/pull/33030)

diff --git a/crypto/armcap.c b/crypto/armcap.c
index f4f6b0d7f9..82482a2e10 100644
--- a/crypto/armcap.c
+++ b/crypto/armcap.c
@@ -254,6 +254,19 @@ static unsigned int arm_probe_for(void (*probe)(void), volatile unsigned int val
 }
 #endif

+#ifdef __aarch64__
+static inline void arm64_setup_rsa_neonized(void)
+{
+    if (OPENSSL_armcap_P & ARMV8_CPUID)
+        OPENSSL_arm_midr = _armv8_cpuid_probe();
+
+    if ((OPENSSL_armcap_P & ARMV7_NEON)
+        && (MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
+            || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)))
+        OPENSSL_armv8_rsa_neonized = 1;
+}
+#endif
+
 void OPENSSL_cpuid_setup(void)
 {
     const char *e;
@@ -271,6 +284,11 @@ void OPENSSL_cpuid_setup(void)

     if ((e = getenv("OPENSSL_armcap"))) {
         OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
+
+#ifdef __aarch64__
+        arm64_setup_rsa_neonized();
+#endif
+
         return;
     }

@@ -412,13 +430,7 @@ void OPENSSL_cpuid_setup(void)
 #endif /* __APPLE__, OSSL_IMPLEMENT_GETAUXVAL */

 #ifdef __aarch64__
-    if (OPENSSL_armcap_P & ARMV8_CPUID)
-        OPENSSL_arm_midr = _armv8_cpuid_probe();
-
-    if ((OPENSSL_armcap_P & ARMV7_NEON)
-        && (MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
-            || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)))
-        OPENSSL_armv8_rsa_neonized = 1;
+    arm64_setup_rsa_neonized();

     if ((OPENSSL_armcap_P & ARMV8_SHA3)
         && (MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1)