Commit 86acf8f95f for qemu.org

commit 86acf8f95f9b4fd7fab4480601fb175361ec03cc
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Fri Aug 28 09:15:31 2026 -0700

    tcg/loongarch64: Import SLADD insns

    Reviewed-by: Matt Turner <mattst88@gmail.com>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc
index e907fc755f..ececc6a3dd 100644
--- a/tcg/loongarch64/tcg-insn-defs.c.inc
+++ b/tcg/loongarch64/tcg-insn-defs.c.inc
@@ -4,7 +4,7 @@
  *
  * This file is auto-generated by genqemutcgdefs from
  * https://github.com/loongson-community/loongarch-opcodes,
- * from commit 1b95bb8c443ad71e266120fd97bd227df2d8ecfc.
+ * from commit 2d84c975e8894afc8b3ee9b8559f10308a658440.
  * DO NOT EDIT.
  */

@@ -24,6 +24,7 @@ typedef enum {
     OPC_REVBIT_D = 0x00005400,
     OPC_SEXT_H = 0x00005800,
     OPC_SEXT_B = 0x00005c00,
+    OPC_SLADD_W = 0x00040000,
     OPC_ADD_W = 0x00100000,
     OPC_ADD_D = 0x00108000,
     OPC_SUB_W = 0x00110000,
@@ -62,6 +63,7 @@ typedef enum {
     OPC_MOD_D = 0x00228000,
     OPC_DIV_DU = 0x00230000,
     OPC_MOD_DU = 0x00238000,
+    OPC_SLADD_D = 0x002c0000,
     OPC_SLLI_W = 0x00408000,
     OPC_SLLI_D = 0x00410000,
     OPC_SRLI_W = 0x00448000,
@@ -619,6 +621,18 @@ encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k)
     return encode_djk_slots(opc, d, j, k);
 }

+static int32_t __attribute__((unused)) encode_djkua2_insn(LoongArchInsn opc,
+                                                          TCGReg d, TCGReg j,
+                                                          TCGReg k,
+                                                          uint32_t ua2)
+{
+    tcg_debug_assert(d >= 0 && d <= 0x1f);
+    tcg_debug_assert(j >= 0 && j <= 0x1f);
+    tcg_debug_assert(k >= 0 && k <= 0x1f);
+    tcg_debug_assert(ua2 <= 0x3);
+    return encode_djka_slots(opc, d, j, k, ua2);
+}
+
 static int32_t __attribute__((unused))
 encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk12)
 {
@@ -1426,6 +1440,13 @@ static void __attribute__((unused)) tcg_out_opc_sext_b(TCGContext *s, TCGReg d,
     tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j));
 }

+/* Emits the `sladd.w d, j, k, ua2` instruction.  */
+static void __attribute__((unused))
+tcg_out_opc_sladd_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k, uint32_t ua2)
+{
+    tcg_out32(s, encode_djkua2_insn(OPC_SLADD_W, d, j, k, ua2));
+}
+
 /* Emits the `add.w d, j, k` instruction.  */
 static void __attribute__((unused)) tcg_out_opc_add_w(TCGContext *s, TCGReg d,
                                                       TCGReg j, TCGReg k)
@@ -1692,6 +1713,13 @@ static void __attribute__((unused)) tcg_out_opc_mod_du(TCGContext *s, TCGReg d,
     tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k));
 }

+/* Emits the `sladd.d d, j, k, ua2` instruction.  */
+static void __attribute__((unused))
+tcg_out_opc_sladd_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k, uint32_t ua2)
+{
+    tcg_out32(s, encode_djkua2_insn(OPC_SLADD_D, d, j, k, ua2));
+}
+
 /* Emits the `slli.w d, j, uk5` instruction.  */
 static void __attribute__((unused)) tcg_out_opc_slli_w(TCGContext *s, TCGReg d,
                                                        TCGReg j, uint32_t uk5)