Commit a8653f40fa for qemu.org

commit a8653f40fa64b770360ba3a13aee7c9451223a11
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date:   Tue Sep 29 21:24:32 2026 +0000

    target/mips: Sign-extend the SRAV operand

    SRAV operates on the low-order 32-bit word of its source and
    sign-extends the shifted result. Sign-extend the source before
    shifting to make results deterministic when the source register
    is not already sign-extended.

    Fixes: 48d38ca52b6 ("Switch most MIPS logical and arithmetic  instructions to TCG")
    Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Acked-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Link: https://lore.kernel.org/qemu-devel/20260929212439.110454-18-pierrick.bouvier@oss.qualcomm.com
    Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index e3467d1525..936f8c4edd 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2853,6 +2853,7 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
         tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
         break;
     case OPC_SRAV:
+        tcg_gen_ext32s_tl(t1, t1);
         tcg_gen_andi_tl(t0, t0, 0x1f);
         tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
         break;