Commit c09348f3d2 for qemu.org

commit c09348f3d240eba2521d46a275806fbf49791ac0
Author: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Date:   Mon Sep 28 17:11:02 2026 -0300

    target/riscv/cpu.c: remove 'bare' condition for .profile

    We want to configure other CPU types to use profiles as an alternative
    to adding every profile extension explicitly, i.e. a profile is nothing
    more than an extension bundle.

    This means that a vendor CPU can set .profile=rva23s64 while having the
    same handling as any other vendor CPU. Same thing with all other CPU
    types.

    Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Reviewed-by: Chao Liu <chao.liu@processmission.com>
    Reviewed-by: Sunil V L <sunilvl@oss.qualcomm.com>
    Message-ID: <20260928201107.2049458-2-daniel.barboza@oss.qualcomm.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e3d096802..658a8162dd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3166,7 +3166,6 @@ static void riscv_cpu_class_base_init(ObjectClass *c, const void *data)
         mcc->def->bare |= def->bare;
         if (def->profile) {
             assert(profile_extends(def->profile, mcc->def->profile));
-            assert(mcc->def->bare);
             mcc->def->profile = def->profile;
         }
         if (def->misa_mxl_max) {